7d15212b8c
fp16 and bf16 values can be used in GCC's inline assembly using the "w" constraint, which means "VFP floating-point registers d0-d31" - fp16 and bf16 values are stored in S registers (which alias the D registers). This change ensures that LLVM is compatible with GCC for programs that use fp16 and the 'w' constraint. Differential Revision: https://reviews.llvm.org/D135662
61 lines
1.7 KiB
LLVM
61 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=arm -mattr=+armv8.2-a,+fp-armv8,+fullfp16,+bf16,-neon %s -o - | FileCheck %s
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; RUN: llc -mtriple=thumb -mattr=+armv8.2-a,+fp-armv8,+fullfp16,+bf16,-neon %s -o - | FileCheck %s
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define arm_aapcscc half @f_t(half %x) nounwind {
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; CHECK-LABEL: f_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f16 s0, r0
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; CHECK-NEXT: @APP
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; CHECK-NEXT: vsqrt.f16 s0, s0
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; CHECK-NEXT: @NO_APP
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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entry:
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%0 = tail call half asm "vsqrt.f16 $0, $1", "=t,t"(half %x)
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ret half %0
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}
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define arm_aapcscc half @f_w(half %x) nounwind {
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; CHECK-LABEL: f_w:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f16 s0, r0
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; CHECK-NEXT: @APP
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; CHECK-NEXT: vsqrt.f16 s0, s0
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; CHECK-NEXT: @NO_APP
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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entry:
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%0 = tail call half asm "vsqrt.f16 $0, $1", "=w,w"(half %x)
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ret half %0
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}
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define arm_aapcscc bfloat @h_t(bfloat %x) nounwind {
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; CHECK-LABEL: h_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f16 s0, r0
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; CHECK-NEXT: @APP
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; CHECK-NEXT: vmov.f32 s0, s0
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; CHECK-NEXT: @NO_APP
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; CHECK-NEXT: vmov.f16 r0, s0
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; CHECK-NEXT: bx lr
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entry:
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%0 = tail call bfloat asm "vmov.f32 $0, $1", "=t,t"(bfloat %x)
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ret bfloat %0
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}
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define arm_aapcscc bfloat @h_w(bfloat %x) nounwind {
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; CHECK-LABEL: h_w:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f16 s0, r0
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; CHECK-NEXT: @APP
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; CHECK-NEXT: vmov.f32 s0, s0
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; CHECK-NEXT: @NO_APP
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; CHECK-NEXT: vmov.f16 r0, s0
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; CHECK-NEXT: bx lr
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entry:
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%0 = tail call bfloat asm "vmov.f32 $0, $1", "=w,w"(bfloat %x)
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ret bfloat %0
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}
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