4ad517e6b0
CSKY arch has multiple FPU instruction versions such as FPU, FPUv2 and FPUv3 to implement floating operations. For now, we just only support FPUv2 and FPUv3. It includes the encoding, asm parsing of instructions and codegen of DAG nodes.
235 lines
6.4 KiB
LLVM
235 lines
6.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv2_sf -mattr=+fpuv2_df | FileCheck %s --check-prefix=CHECK-DF
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; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv3_sf -mattr=+fpuv3_df | FileCheck %s --check-prefix=CHECK-DF2
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define double @FADD_DOUBLE(double %x, double %y) {
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; CHECK-DF-LABEL: FADD_DOUBLE:
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; CHECK-DF: # %bb.0: # %entry
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; CHECK-DF-NEXT: faddd vr0, vr1, vr0
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; CHECK-DF-NEXT: rts16
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;
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; CHECK-DF2-LABEL: FADD_DOUBLE:
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; CHECK-DF2: # %bb.0: # %entry
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; CHECK-DF2-NEXT: fadd.64 vr0, vr1, vr0
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; CHECK-DF2-NEXT: rts16
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entry:
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%fadd = fadd double %y, %x
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ret double %fadd
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}
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define double @FADD_DOUBLE_I(double %x) {
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; CHECK-DF-LABEL: FADD_DOUBLE_I:
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; CHECK-DF: # %bb.0: # %entry
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; CHECK-DF-NEXT: grs32 a0, .LCPI1_0
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; CHECK-DF-NEXT: fldd vr1, (a0, 0)
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; CHECK-DF-NEXT: faddd vr0, vr0, vr1
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; CHECK-DF-NEXT: rts16
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; CHECK-DF-NEXT: .p2align 1
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; CHECK-DF-NEXT: # %bb.1:
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; CHECK-DF-NEXT: .p2align 2
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; CHECK-DF-NEXT: .LCPI1_0:
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; CHECK-DF-NEXT: .quad 0xbff0000000000000 # double -1
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;
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; CHECK-DF2-LABEL: FADD_DOUBLE_I:
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; CHECK-DF2: # %bb.0: # %entry
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; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI1_0]
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; CHECK-DF2-NEXT: fadd.64 vr0, vr0, vr1
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; CHECK-DF2-NEXT: rts16
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; CHECK-DF2-NEXT: .p2align 1
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; CHECK-DF2-NEXT: # %bb.1:
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; CHECK-DF2-NEXT: .p2align 2
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; CHECK-DF2-NEXT: .LCPI1_0:
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; CHECK-DF2-NEXT: .quad 0xbff0000000000000 # double -1
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entry:
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%fadd = fadd double %x, -1.0
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ret double %fadd
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}
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define double @FSUB_DOUBLE(double %x, double %y) {
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; CHECK-DF-LABEL: FSUB_DOUBLE:
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; CHECK-DF: # %bb.0: # %entry
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; CHECK-DF-NEXT: fsubd vr0, vr1, vr0
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; CHECK-DF-NEXT: rts16
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;
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; CHECK-DF2-LABEL: FSUB_DOUBLE:
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; CHECK-DF2: # %bb.0: # %entry
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; CHECK-DF2-NEXT: fsub.64 vr0, vr1, vr0
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; CHECK-DF2-NEXT: rts16
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entry:
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%fsub = fsub double %y, %x
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ret double %fsub
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}
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define double @FSUB_DOUBLE_I(double %x) {
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;
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; CHECK-DF-LABEL: FSUB_DOUBLE_I:
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; CHECK-DF: # %bb.0: # %entry
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; CHECK-DF-NEXT: grs32 a0, .LCPI3_0
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; CHECK-DF-NEXT: fldd vr1, (a0, 0)
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; CHECK-DF-NEXT: faddd vr0, vr0, vr1
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; CHECK-DF-NEXT: rts16
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; CHECK-DF-NEXT: .p2align 1
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; CHECK-DF-NEXT: # %bb.1:
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; CHECK-DF-NEXT: .p2align 2
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; CHECK-DF-NEXT: .LCPI3_0:
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; CHECK-DF-NEXT: .quad 0x3ff0000000000000 # double 1
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;
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; CHECK-DF2-LABEL: FSUB_DOUBLE_I:
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; CHECK-DF2: # %bb.0: # %entry
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; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI3_0]
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; CHECK-DF2-NEXT: fadd.64 vr0, vr0, vr1
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; CHECK-DF2-NEXT: rts16
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; CHECK-DF2-NEXT: .p2align 1
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; CHECK-DF2-NEXT: # %bb.1:
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; CHECK-DF2-NEXT: .p2align 2
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; CHECK-DF2-NEXT: .LCPI3_0:
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; CHECK-DF2-NEXT: .quad 0x3ff0000000000000 # double 1
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entry:
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%fsub = fsub double %x, -1.0
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ret double %fsub
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}
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define double @FMUL_DOUBLE(double %x, double %y) {
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;
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; CHECK-DF-LABEL: FMUL_DOUBLE:
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; CHECK-DF: # %bb.0: # %entry
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; CHECK-DF-NEXT: fmuld vr0, vr1, vr0
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; CHECK-DF-NEXT: rts16
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;
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; CHECK-DF2-LABEL: FMUL_DOUBLE:
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; CHECK-DF2: # %bb.0: # %entry
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; CHECK-DF2-NEXT: fmul.64 vr0, vr1, vr0
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; CHECK-DF2-NEXT: rts16
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entry:
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%fmul = fmul double %y, %x
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ret double %fmul
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}
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define double @FMUL_DOUBLE_I(double %x) {
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;
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; CHECK-DF-LABEL: FMUL_DOUBLE_I:
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; CHECK-DF: # %bb.0: # %entry
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; CHECK-DF-NEXT: grs32 a0, .LCPI5_0
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; CHECK-DF-NEXT: fldd vr1, (a0, 0)
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; CHECK-DF-NEXT: fmuld vr0, vr0, vr1
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; CHECK-DF-NEXT: rts16
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; CHECK-DF-NEXT: .p2align 1
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; CHECK-DF-NEXT: # %bb.1:
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; CHECK-DF-NEXT: .p2align 2
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; CHECK-DF-NEXT: .LCPI5_0:
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; CHECK-DF-NEXT: .quad 0xc01c000000000000 # double -7
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;
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; CHECK-DF2-LABEL: FMUL_DOUBLE_I:
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; CHECK-DF2: # %bb.0: # %entry
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; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI5_0]
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; CHECK-DF2-NEXT: fmul.64 vr0, vr0, vr1
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; CHECK-DF2-NEXT: rts16
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; CHECK-DF2-NEXT: .p2align 1
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; CHECK-DF2-NEXT: # %bb.1:
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; CHECK-DF2-NEXT: .p2align 2
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; CHECK-DF2-NEXT: .LCPI5_0:
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; CHECK-DF2-NEXT: .quad 0xc01c000000000000 # double -7
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entry:
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%fmul = fmul double %x, -7.0
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ret double %fmul
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}
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define double @FDIV_DOUBLE(double %x, double %y) {
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;
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;
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; CHECK-DF-LABEL: FDIV_DOUBLE:
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; CHECK-DF: # %bb.0: # %entry
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; CHECK-DF-NEXT: fdivd vr0, vr1, vr0
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; CHECK-DF-NEXT: rts16
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;
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; CHECK-DF2-LABEL: FDIV_DOUBLE:
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; CHECK-DF2: # %bb.0: # %entry
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; CHECK-DF2-NEXT: fdiv.64 vr0, vr1, vr0
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; CHECK-DF2-NEXT: rts16
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entry:
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%fdiv = fdiv double %y, %x
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ret double %fdiv
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}
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define double @FDIV_DOUBLE_I(double %x) {
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;
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; CHECK-DF-LABEL: FDIV_DOUBLE_I:
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; CHECK-DF: # %bb.0: # %entry
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; CHECK-DF-NEXT: grs32 a0, .LCPI7_0
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; CHECK-DF-NEXT: fldd vr1, (a0, 0)
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; CHECK-DF-NEXT: fdivd vr0, vr0, vr1
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; CHECK-DF-NEXT: rts16
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; CHECK-DF-NEXT: .p2align 1
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; CHECK-DF-NEXT: # %bb.1:
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; CHECK-DF-NEXT: .p2align 2
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; CHECK-DF-NEXT: .LCPI7_0:
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; CHECK-DF-NEXT: .quad 0xc01c000000000000 # double -7
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;
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; CHECK-DF2-LABEL: FDIV_DOUBLE_I:
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; CHECK-DF2: # %bb.0: # %entry
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; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI7_0]
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; CHECK-DF2-NEXT: fdiv.64 vr0, vr0, vr1
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; CHECK-DF2-NEXT: rts16
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; CHECK-DF2-NEXT: .p2align 1
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; CHECK-DF2-NEXT: # %bb.1:
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; CHECK-DF2-NEXT: .p2align 2
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; CHECK-DF2-NEXT: .LCPI7_0:
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; CHECK-DF2-NEXT: .quad 0xc01c000000000000 # double -7
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entry:
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%fdiv = fdiv double %x, -7.0
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ret double %fdiv
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}
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define double @FNEG_DOUBLE(double %x) {
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;
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; CHECK-DF-LABEL: FNEG_DOUBLE:
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; CHECK-DF: # %bb.0: # %entry
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; CHECK-DF-NEXT: fnegd vr0, vr0
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; CHECK-DF-NEXT: rts16
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;
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; CHECK-DF2-LABEL: FNEG_DOUBLE:
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; CHECK-DF2: # %bb.0: # %entry
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; CHECK-DF2-NEXT: fneg.64 vr0, vr0
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; CHECK-DF2-NEXT: rts16
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entry:
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%fneg = fneg double %x
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ret double %fneg
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}
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; double --> float
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define float @fptruncR_double_0(double %x) {
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;
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; CHECK-DF-LABEL: fptruncR_double_0:
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; CHECK-DF: # %bb.0: # %entry
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; CHECK-DF-NEXT: fdtos vr0, vr0
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; CHECK-DF-NEXT: rts16
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;
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; CHECK-DF2-LABEL: fptruncR_double_0:
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; CHECK-DF2: # %bb.0: # %entry
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; CHECK-DF2-NEXT: fdtos vr0, vr0
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; CHECK-DF2-NEXT: rts16
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entry:
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%fptrunc = fptrunc double %x to float
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ret float %fptrunc
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}
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define double @fpextR_double_0(float %x) {
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;
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; CHECK-DF-LABEL: fpextR_double_0:
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; CHECK-DF: # %bb.0: # %entry
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; CHECK-DF-NEXT: fstod vr0, vr0
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; CHECK-DF-NEXT: rts16
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;
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; CHECK-DF2-LABEL: fpextR_double_0:
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; CHECK-DF2: # %bb.0: # %entry
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; CHECK-DF2-NEXT: fstod vr0, vr0
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; CHECK-DF2-NEXT: rts16
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entry:
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%fpext = fpext float %x to double
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ret double %fpext
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}
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