57ad3f1dc6
When the branch target is out of the range represented by the current branch instruction's immediate, branch relaxation is required. There are three types of immediate for branch instructions on LoongArch, including simm16, simm21 and simm26. And the real branch target address is PC + sext(simmXX << 2). In addition, the indirect branch way is implemented to support larger branch target. BranchRelaxation pass calls `RenumberBlocks` to renumber all of the machine basic blocks in the function. So the machine basic blocks number changed in some test cases. Differential Revision: https://reviews.llvm.org/D137233
152 lines
4.7 KiB
LLVM
152 lines
4.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc --mtriple=loongarch32 --min-jump-table-entries=5 < %s \
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; RUN: | FileCheck %s --check-prefix=LA32
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; RUN: llc --mtriple=loongarch64 --min-jump-table-entries=5 < %s \
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; RUN: | FileCheck %s --check-prefix=LA64
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; RUN: llc --mtriple=loongarch32 --min-jump-table-entries=4 < %s \
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; RUN: | FileCheck %s --check-prefix=LA32-JT
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; RUN: llc --mtriple=loongarch64 --min-jump-table-entries=4 < %s \
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; RUN: | FileCheck %s --check-prefix=LA64-JT
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;; The default mininum number of entries to use a jump table is 4.
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;;
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;; Note: The parameter `--min-jump-table-entries` will have no effect once we
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;; have set the default value using `setMinimumJumpTableEntries`.
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define void @switch_4_arms(i32 %in, ptr %out) nounwind {
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; LA32-LABEL: switch_4_arms:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: ori $a2, $zero, 2
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; LA32-NEXT: blt $a2, $a0, .LBB0_4
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; LA32-NEXT: # %bb.1: # %entry
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; LA32-NEXT: ori $a3, $zero, 1
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; LA32-NEXT: beq $a0, $a3, .LBB0_7
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; LA32-NEXT: # %bb.2: # %entry
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; LA32-NEXT: bne $a0, $a2, .LBB0_9
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; LA32-NEXT: # %bb.3: # %bb2
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; LA32-NEXT: ori $a0, $zero, 3
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; LA32-NEXT: st.w $a0, $a1, 0
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; LA32-NEXT: ret
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; LA32-NEXT: .LBB0_4: # %entry
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; LA32-NEXT: ori $a3, $zero, 3
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; LA32-NEXT: beq $a0, $a3, .LBB0_8
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; LA32-NEXT: # %bb.5: # %entry
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; LA32-NEXT: ori $a2, $zero, 4
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; LA32-NEXT: bne $a0, $a2, .LBB0_9
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; LA32-NEXT: # %bb.6: # %bb4
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; LA32-NEXT: ori $a0, $zero, 1
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; LA32-NEXT: st.w $a0, $a1, 0
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; LA32-NEXT: ret
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; LA32-NEXT: .LBB0_7: # %bb1
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; LA32-NEXT: ori $a0, $zero, 4
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; LA32-NEXT: st.w $a0, $a1, 0
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; LA32-NEXT: ret
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; LA32-NEXT: .LBB0_8: # %bb3
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; LA32-NEXT: st.w $a2, $a1, 0
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; LA32-NEXT: .LBB0_9: # %exit
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; LA32-NEXT: ret
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;
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; LA64-LABEL: switch_4_arms:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: bstrpick.d $a0, $a0, 31, 0
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; LA64-NEXT: ori $a2, $zero, 2
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; LA64-NEXT: blt $a2, $a0, .LBB0_4
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; LA64-NEXT: # %bb.1: # %entry
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; LA64-NEXT: ori $a3, $zero, 1
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; LA64-NEXT: beq $a0, $a3, .LBB0_7
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; LA64-NEXT: # %bb.2: # %entry
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; LA64-NEXT: bne $a0, $a2, .LBB0_9
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; LA64-NEXT: # %bb.3: # %bb2
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; LA64-NEXT: ori $a0, $zero, 3
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; LA64-NEXT: st.w $a0, $a1, 0
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; LA64-NEXT: ret
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; LA64-NEXT: .LBB0_4: # %entry
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; LA64-NEXT: ori $a3, $zero, 3
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; LA64-NEXT: beq $a0, $a3, .LBB0_8
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; LA64-NEXT: # %bb.5: # %entry
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; LA64-NEXT: ori $a2, $zero, 4
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; LA64-NEXT: bne $a0, $a2, .LBB0_9
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; LA64-NEXT: # %bb.6: # %bb4
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; LA64-NEXT: ori $a0, $zero, 1
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; LA64-NEXT: st.w $a0, $a1, 0
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; LA64-NEXT: ret
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; LA64-NEXT: .LBB0_7: # %bb1
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; LA64-NEXT: ori $a0, $zero, 4
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; LA64-NEXT: st.w $a0, $a1, 0
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; LA64-NEXT: ret
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; LA64-NEXT: .LBB0_8: # %bb3
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; LA64-NEXT: st.w $a2, $a1, 0
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; LA64-NEXT: .LBB0_9: # %exit
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; LA64-NEXT: ret
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;
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; LA32-JT-LABEL: switch_4_arms:
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; LA32-JT: # %bb.0: # %entry
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; LA32-JT-NEXT: addi.w $a2, $a0, -1
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; LA32-JT-NEXT: ori $a0, $zero, 3
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; LA32-JT-NEXT: bltu $a0, $a2, .LBB0_6
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; LA32-JT-NEXT: # %bb.1: # %entry
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; LA32-JT-NEXT: pcalau12i $a3, %pc_hi20(.LJTI0_0)
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; LA32-JT-NEXT: addi.w $a3, $a3, %pc_lo12(.LJTI0_0)
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; LA32-JT-NEXT: alsl.w $a2, $a2, $a3, 2
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; LA32-JT-NEXT: ld.w $a2, $a2, 0
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; LA32-JT-NEXT: jr $a2
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; LA32-JT-NEXT: .LBB0_2: # %bb1
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; LA32-JT-NEXT: ori $a0, $zero, 4
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; LA32-JT-NEXT: b .LBB0_5
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; LA32-JT-NEXT: .LBB0_3: # %bb3
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; LA32-JT-NEXT: ori $a0, $zero, 2
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; LA32-JT-NEXT: b .LBB0_5
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; LA32-JT-NEXT: .LBB0_4: # %bb4
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; LA32-JT-NEXT: ori $a0, $zero, 1
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; LA32-JT-NEXT: .LBB0_5: # %exit
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; LA32-JT-NEXT: st.w $a0, $a1, 0
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; LA32-JT-NEXT: .LBB0_6: # %exit
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; LA32-JT-NEXT: ret
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;
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; LA64-JT-LABEL: switch_4_arms:
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; LA64-JT: # %bb.0: # %entry
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; LA64-JT-NEXT: bstrpick.d $a0, $a0, 31, 0
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; LA64-JT-NEXT: addi.d $a2, $a0, -1
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; LA64-JT-NEXT: ori $a0, $zero, 3
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; LA64-JT-NEXT: bltu $a0, $a2, .LBB0_6
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; LA64-JT-NEXT: # %bb.1: # %entry
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; LA64-JT-NEXT: slli.d $a2, $a2, 3
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; LA64-JT-NEXT: pcalau12i $a3, %pc_hi20(.LJTI0_0)
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; LA64-JT-NEXT: addi.d $a3, $a3, %pc_lo12(.LJTI0_0)
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; LA64-JT-NEXT: ldx.d $a2, $a2, $a3
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; LA64-JT-NEXT: jr $a2
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; LA64-JT-NEXT: .LBB0_2: # %bb1
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; LA64-JT-NEXT: ori $a0, $zero, 4
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; LA64-JT-NEXT: b .LBB0_5
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; LA64-JT-NEXT: .LBB0_3: # %bb3
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; LA64-JT-NEXT: ori $a0, $zero, 2
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; LA64-JT-NEXT: b .LBB0_5
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; LA64-JT-NEXT: .LBB0_4: # %bb4
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; LA64-JT-NEXT: ori $a0, $zero, 1
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; LA64-JT-NEXT: .LBB0_5: # %exit
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; LA64-JT-NEXT: st.w $a0, $a1, 0
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; LA64-JT-NEXT: .LBB0_6: # %exit
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; LA64-JT-NEXT: ret
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entry:
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switch i32 %in, label %exit [
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i32 1, label %bb1
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i32 2, label %bb2
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i32 3, label %bb3
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i32 4, label %bb4
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]
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bb1:
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store i32 4, ptr %out
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br label %exit
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bb2:
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store i32 3, ptr %out
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br label %exit
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bb3:
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store i32 2, ptr %out
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br label %exit
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bb4:
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store i32 1, ptr %out
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br label %exit
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exit:
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ret void
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}
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