48904e9452
Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
224 lines
5.8 KiB
YAML
224 lines
5.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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--- |
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define void @and_i32() {entry: ret void}
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define void @or_i32() {entry: ret void}
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define void @xor_i32() {entry: ret void}
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define void @shl(i32) {entry: ret void}
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define void @ashr(i32) {entry: ret void}
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define void @lshr(i32) {entry: ret void}
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define void @shlv(i32, i32) {entry: ret void}
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define void @ashrv(i32, i32) {entry: ret void}
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define void @lshrv(i32, i32) {entry: ret void}
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...
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---
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name: and_i32
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: and_i32
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
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; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY1]], [[COPY]]
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; MIPS32: $v0 = COPY [[AND]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(s32) = COPY $a0
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%1:_(s32) = COPY $a1
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%2:_(s32) = G_AND %1, %0
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: or_i32
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: or_i32
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
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; MIPS32: [[OR:%[0-9]+]]:gprb(s32) = G_OR [[COPY1]], [[COPY]]
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; MIPS32: $v0 = COPY [[OR]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(s32) = COPY $a0
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%1:_(s32) = COPY $a1
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%2:_(s32) = G_OR %1, %0
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: xor_i32
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: xor_i32
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
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; MIPS32: [[XOR:%[0-9]+]]:gprb(s32) = G_XOR [[COPY1]], [[COPY]]
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; MIPS32: $v0 = COPY [[XOR]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(s32) = COPY $a0
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%1:_(s32) = COPY $a1
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%2:_(s32) = G_XOR %1, %0
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: shl
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: shl
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
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; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
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; MIPS32: [[SHL:%[0-9]+]]:gprb(s32) = G_SHL [[COPY]], [[C]]
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; MIPS32: $v0 = COPY [[SHL]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(s32) = COPY $a0
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%1:_(s32) = G_CONSTANT i32 1
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%2:_(s32) = G_SHL %0, %1
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: ashr
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: ashr
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
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; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
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; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[COPY]], [[C]]
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; MIPS32: $v0 = COPY [[ASHR]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(s32) = COPY $a0
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%1:_(s32) = G_CONSTANT i32 1
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%2:_(s32) = G_ASHR %0, %1
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: lshr
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: lshr
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
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; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
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; MIPS32: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[COPY]], [[C]]
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; MIPS32: $v0 = COPY [[LSHR]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(s32) = COPY $a0
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%1:_(s32) = G_CONSTANT i32 1
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%2:_(s32) = G_LSHR %0, %1
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: shlv
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: shlv
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
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; MIPS32: [[SHL:%[0-9]+]]:gprb(s32) = G_SHL [[COPY]], [[COPY1]]
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; MIPS32: $v0 = COPY [[SHL]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(s32) = COPY $a0
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%1:_(s32) = COPY $a1
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%2:_(s32) = G_SHL %0, %1
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: ashrv
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: ashrv
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
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; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[COPY]], [[COPY1]]
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; MIPS32: $v0 = COPY [[ASHR]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(s32) = COPY $a0
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%1:_(s32) = COPY $a1
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%2:_(s32) = G_ASHR %0, %1
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: lshrv
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: lshrv
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
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; MIPS32: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[COPY]], [[COPY1]]
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; MIPS32: $v0 = COPY [[LSHR]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(s32) = COPY $a0
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%1:_(s32) = COPY $a1
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%2:_(s32) = G_LSHR %0, %1
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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