eb7d16ea25
mflr is kind of expensive on Power version smaller than 10, so we should schedule the store for the mflr's def away from mflr. In epilogue, the expensive mtlr has no user for its def, so it doesn't matter that the load and the mtlr are back-to-back. Reviewed By: RolandF Differential Revision: https://reviews.llvm.org/D137423
117 lines
4.2 KiB
LLVM
117 lines
4.2 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
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; RUN: -mattr=-altivec -filetype=obj -xcoff-traceback-table=false -o %t.o < %s
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; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=32-SYM %s
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; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck \
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; RUN: --check-prefix=32-REL %s
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; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=32-DIS %s
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; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff \
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; RUN: -mcpu=pwr4 -mattr=-altivec < %s | FileCheck %s
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;; FIXME: currently only fileHeader and sectionHeaders are supported in XCOFF64.
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; Test verifies:
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; If there exists a user-defined function whose name is the same as the
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; "memcpy" ExternalSymbol's, we pick up the user-defined version, even if this
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; may lead to some undefined behavior.
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define dso_local signext i32 @memcpy(ptr %destination, i32 signext %num) {
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entry:
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ret i32 3
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}
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define void @call_memcpy(ptr %p, ptr %q, i32 %n) {
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entry:
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call void @llvm.memcpy.p0.p0.i32(ptr %p, ptr %q, i32 %n, i1 false)
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ret void
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}
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declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture readonly, i32, i1)
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; This test check
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; 1. The symbol table for .o file to verify .memcpy is a defined external label.
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; 2. There is no relocation associated with the call, since callee is defined.
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; 3. Branch instruction in raw data is branching back to the right callee location.
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; CHECK-NOT: .extern .memcpy
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; 32-SYM: Symbol {{[{][[:space:]] *}}Index: [[#Index:]]{{[[:space:]] *}}Name: .memcpy
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; 32-SYM-NEXT: Value (RelocatableAddress): 0x0
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; 32-SYM-NEXT: Section: .text
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; 32-SYM-NEXT: Type: 0x0
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; 32-SYM-NEXT: StorageClass: C_EXT (0x2)
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; 32-SYM-NEXT: NumberOfAuxEntries: 1
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; 32-SYM-NEXT: CSECT Auxiliary Entry {
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; 32-SYM-NEXT: Index: 4
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; 32-SYM-NEXT: ContainingCsectSymbolIndex: 1
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; 32-SYM-NEXT: ParameterHashIndex: 0x0
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; 32-SYM-NEXT: TypeChkSectNum: 0x0
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; 32-SYM-NEXT: SymbolAlignmentLog2: 0
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; 32-SYM-NEXT: SymbolType: XTY_LD (0x2)
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; 32-SYM-NEXT: StorageMappingClass: XMC_PR (0x0)
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; 32-SYM-NEXT: StabInfoIndex: 0x0
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; 32-SYM-NEXT: StabSectNum: 0x0
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; 32-SYM-NEXT: }
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; 32-SYM-NEXT: }
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; 32-SYM-NOT: .memcpy
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; 32-REL: Relocations [
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; 32-REL-NEXT: Section (index: 2) .data {
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; 32-REL-NEXT: Relocation {
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; 32-REL-NEXT: Virtual Address: 0x34
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; 32-REL-NEXT: Symbol: .memcpy (3)
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; 32-REL-NEXT: IsSigned: No
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; 32-REL-NEXT: FixupBitValue: 0
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; 32-REL-NEXT: Length: 32
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; 32-REL-NEXT: Type: R_POS (0x0)
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; 32-REL-NEXT: }
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; 32-REL-NEXT: Relocation {
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; 32-REL-NEXT: Virtual Address: 0x38
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; 32-REL-NEXT: Symbol: TOC (11)
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; 32-REL-NEXT: IsSigned: No
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; 32-REL-NEXT: FixupBitValue: 0
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; 32-REL-NEXT: Length: 32
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; 32-REL-NEXT: Type: R_POS (0x0)
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; 32-REL-NEXT: }
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; 32-REL-NEXT: Relocation {
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; 32-REL-NEXT: Virtual Address: 0x40
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; 32-REL-NEXT: Symbol: .call_memcpy (5)
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; 32-REL-NEXT: IsSigned: No
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; 32-REL-NEXT: FixupBitValue: 0
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; 32-REL-NEXT: Length: 32
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; 32-REL-NEXT: Type: R_POS (0x0)
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; 32-REL-NEXT: }
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; 32-REL-NEXT: Relocation {
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; 32-REL-NEXT: Virtual Address: 0x44
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; 32-REL-NEXT: Symbol: TOC (11)
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; 32-REL-NEXT: IsSigned: No
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; 32-REL-NEXT: FixupBitValue: 0
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; 32-REL-NEXT: Length: 32
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; 32-REL-NEXT: Type: R_POS (0x0)
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; 32-REL-NEXT: }
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; 32-REL-NEXT: }
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; 32-REL-NEXT: ]
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; 32-REL-NOT: Type: R_RBR (0x1A)
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; 32-DIS: Disassembly of section .text:
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; 32-DIS: 00000000 <.memcpy>:
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; 32-DIS-NEXT: 0: 38 60 00 03 li 3, 3
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; 32-DIS-NEXT: 4: 4e 80 00 20 blr
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; 32-DIS-NEXT: 8: 60 00 00 00 nop
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; 32-DIS-NEXT: c: 60 00 00 00 nop
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; 32-DIS: 00000010 <.call_memcpy>:
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; 32-DIS-NEXT: 10: 7c 08 02 a6 mflr 0
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; 32-DIS-NEXT: 14: 94 21 ff c0 stwu 1, -64(1)
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; 32-DIS-NEXT: 18: 90 01 00 48 stw 0, 72(1)
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; 32-DIS-NEXT: 1c: 4b ff ff e5 bl 0x0
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; 32-DIS-NEXT: 20: 60 00 00 00 nop
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; 32-DIS-NEXT: 24: 38 21 00 40 addi 1, 1, 64
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; 32-DIS-NEXT: 28: 80 01 00 08 lwz 0, 8(1)
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; 32-DIS-NEXT: 2c: 7c 08 03 a6 mtlr 0
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; 32-DIS-NEXT: 30: 4e 80 00 20 blr
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