eb7d16ea25
mflr is kind of expensive on Power version smaller than 10, so we should schedule the store for the mflr's def away from mflr. In epilogue, the expensive mtlr has no user for its def, so it doesn't matter that the load and the mtlr are back-to-back. Reviewed By: RolandF Differential Revision: https://reviews.llvm.org/D137423
99 lines
3.5 KiB
LLVM
99 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \
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; RUN: -vec-extabi -mtriple powerpc-ibm-aix-xcoff < %s | \
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; RUN: FileCheck %s --check-prefixes=32BIT,LITERAL
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \
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; RUN: -vec-extabi -mtriple powerpc64-ibm-aix-xcoff < %s | \
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; RUN: FileCheck %s --check-prefixes=64BIT,LITERAL
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define dso_local i32 @vec_caller() {
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; LITERAL: L..CPI0_0:
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; LITERAL-NEXT: .vbyte 4, 53
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; LITERAL-NEXT: .vbyte 4, 54
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; LITERAL-NEXT: .vbyte 4, 55
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; LITERAL-NEXT: .vbyte 4, 56
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; LITERAL-NEXT: L..CPI0_1:
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; LITERAL-NEXT: .vbyte 4, 49
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; LITERAL-NEXT: .vbyte 4, 50
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; LITERAL-NEXT: .vbyte 4, 51
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; LITERAL-NEXT: .vbyte 4, 52
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; 32BIT-LABEL: vec_caller:
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; 32BIT: # %bb.0: # %entry
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; 32BIT-NEXT: mflr 0
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; 32BIT-NEXT: stwu 1, -64(1)
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; 32BIT-NEXT: lwz 3, L..C0(2)
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; 32BIT-NEXT: lwz 4, L..C1(2)
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; 32BIT-NEXT: xxlxor 34, 34, 34
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; 32BIT-NEXT: stw 0, 72(1)
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; 32BIT-NEXT: xxlxor 35, 35, 35
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; 32BIT-NEXT: xxlxor 36, 36, 36
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; 32BIT-NEXT: lxvw4x 0, 0, 3
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; 32BIT-NEXT: lxvw4x 1, 0, 4
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; 32BIT-NEXT: xxlxor 37, 37, 37
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; 32BIT-NEXT: li 3, 48
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; 32BIT-NEXT: xxlxor 38, 38, 38
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; 32BIT-NEXT: li 4, 32
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; 32BIT-NEXT: xxlxor 39, 39, 39
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; 32BIT-NEXT: xxlxor 40, 40, 40
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; 32BIT-NEXT: stxvw4x 0, 1, 3
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; 32BIT-NEXT: xxlxor 41, 41, 41
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; 32BIT-NEXT: stxvw4x 1, 1, 4
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; 32BIT-NEXT: xxlxor 42, 42, 42
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; 32BIT-NEXT: xxlxor 43, 43, 43
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; 32BIT-NEXT: xxlxor 44, 44, 44
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; 32BIT-NEXT: xxlxor 45, 45, 45
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; 32BIT-NEXT: bl .vec_callee_stack[PR]
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; 32BIT-NEXT: nop
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; 32BIT-NEXT: addi 1, 1, 64
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; 32BIT-NEXT: lwz 0, 8(1)
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; 32BIT-NEXT: mtlr 0
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; 32BIT-NEXT: blr
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; 64BIT-LABEL: vec_caller:
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; 64BIT: # %bb.0: # %entry
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; 64BIT-NEXT: mflr 0
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; 64BIT-NEXT: stdu 1, -112(1)
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; 64BIT-NEXT: ld 3, L..C0(2)
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; 64BIT-NEXT: ld 4, L..C1(2)
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; 64BIT-NEXT: xxlxor 34, 34, 34
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; 64BIT-NEXT: std 0, 128(1)
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; 64BIT-NEXT: xxlxor 35, 35, 35
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; 64BIT-NEXT: xxlxor 36, 36, 36
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; 64BIT-NEXT: lxvw4x 0, 0, 3
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; 64BIT-NEXT: lxvw4x 1, 0, 4
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; 64BIT-NEXT: xxlxor 37, 37, 37
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; 64BIT-NEXT: li 3, 64
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; 64BIT-NEXT: xxlxor 38, 38, 38
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; 64BIT-NEXT: li 4, 48
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; 64BIT-NEXT: xxlxor 39, 39, 39
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; 64BIT-NEXT: xxlxor 40, 40, 40
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; 64BIT-NEXT: stxvw4x 0, 1, 3
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; 64BIT-NEXT: xxlxor 41, 41, 41
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; 64BIT-NEXT: stxvw4x 1, 1, 4
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; 64BIT-NEXT: xxlxor 42, 42, 42
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; 64BIT-NEXT: xxlxor 43, 43, 43
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; 64BIT-NEXT: xxlxor 44, 44, 44
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; 64BIT-NEXT: xxlxor 45, 45, 45
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; 64BIT-NEXT: bl .vec_callee_stack[PR]
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; 64BIT-NEXT: nop
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; 64BIT-NEXT: addi 1, 1, 112
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; 64BIT-NEXT: ld 0, 16(1)
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; 64BIT-NEXT: mtlr 0
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; 64BIT-NEXT: blr
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; LITERAL: .toc
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; LITERAL: L..C0:
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; LITERAL-NEXT: .tc L..CPI0_0[TC],L..CPI0_0
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; LITERAL-NEXT: L..C1:
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; LITERAL-NEXT: .tc L..CPI0_1[TC],L..CPI0_1
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entry:
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%call = call i32 @vec_callee_stack(<4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 49, i32 50, i32 51, i32 52>, <4 x i32> <i32 53, i32 54, i32 55, i32 56>)
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ret i32 %call
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}
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declare i32 @vec_callee_stack(...)
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