427fb35192
The LIT test cases were migrated with the script provided by Nikita Popov. Due to the size of the change it is split into several parts. Reviewed By: nemanja, amyk, nikic, PowerPC Differential Revision: https://reviews.llvm.org/D135470
76 lines
3.0 KiB
LLVM
76 lines
3.0 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+power8-vector -mattr=-vsx < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-VSX
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@vsc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16
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@vsc2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16
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@vuc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16
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@vuc2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16
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@res_vll = common global <2 x i64> zeroinitializer, align 16
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@res_vull = common global <2 x i64> zeroinitializer, align 16
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@res_vsc = common global <16 x i8> zeroinitializer, align 16
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@res_vuc = common global <16 x i8> zeroinitializer, align 16
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; Function Attrs: nounwind
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define void @test1() {
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entry:
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%0 = load <16 x i8>, ptr @vsc, align 16
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%1 = load <16 x i8>, ptr @vsc2, align 16
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%2 = call <2 x i64> @llvm.ppc.altivec.vbpermq(<16 x i8> %0, <16 x i8> %1)
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store <2 x i64> %2, ptr @res_vll, align 16
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ret void
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; CHECK-LABEL: @test1
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; CHECK: lvx [[REG1:[0-9]+]], 0, 3
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; CHECK: lvx [[REG2:[0-9]+]], 0, 4
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; CHECK: vbpermq {{[0-9]+}}, [[REG1]], [[REG2]]
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; CHECK-VSX: vbpermq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test2() {
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entry:
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%0 = load <16 x i8>, ptr @vuc, align 16
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%1 = load <16 x i8>, ptr @vuc2, align 16
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%2 = call <2 x i64> @llvm.ppc.altivec.vbpermq(<16 x i8> %0, <16 x i8> %1)
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store <2 x i64> %2, ptr @res_vull, align 16
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ret void
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; CHECK-LABEL: @test2
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; CHECK: lvx [[REG1:[0-9]+]], 0, 3
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; CHECK: lvx [[REG2:[0-9]+]], 0, 4
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; CHECK: vbpermq {{[0-9]+}}, [[REG1]], [[REG2]]
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; CHECK-VSX: vbpermq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test3() {
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entry:
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%0 = load <16 x i8>, ptr @vsc, align 16
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%1 = call <16 x i8> @llvm.ppc.altivec.vgbbd(<16 x i8> %0)
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store <16 x i8> %1, ptr @res_vsc, align 16
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ret void
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; CHECK-LABEL: @test3
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; CHECK: lvx [[REG1:[0-9]+]],
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; CHECK: vgbbd {{[0-9]+}}, [[REG1]]
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; CHECK-VSX: vgbbd {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test4() {
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entry:
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%0 = load <16 x i8>, ptr @vuc, align 16
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%1 = call <16 x i8> @llvm.ppc.altivec.vgbbd(<16 x i8> %0)
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store <16 x i8> %1, ptr @res_vuc, align 16
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ret void
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; CHECK-LABEL: @test4
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; CHECK: lvx [[REG1:[0-9]+]],
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; CHECK: vgbbd {{[0-9]+}}, [[REG1]]
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; CHECK-VSX: vgbbd {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind readnone
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declare <2 x i64> @llvm.ppc.altivec.vbpermq(<16 x i8>, <16 x i8>)
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; Function Attrs: nounwind readnone
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declare <16 x i8> @llvm.ppc.altivec.vgbbd(<16 x i8>)
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