b5e1fc19da
We added a new post-isel CTRLoop pass in D122125. That pass will expand the hardware loop related intrinsic to CTR loop or normal loop based on the loop context. So we don't need to conservatively check the CTR clobber now on the IR level. Reviewed By: lkail Differential Revision: https://reviews.llvm.org/D135847
147 lines
5.0 KiB
LLVM
147 lines
5.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9LE
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; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9BE
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; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8LE
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; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8BE
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declare ppc_fp128 @llvm.fmuladd.ppcf128(ppc_fp128, ppc_fp128, ppc_fp128) #2
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define ppc_fp128 @test_ctr0() {
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; P9LE-LABEL: test_ctr0:
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; P9LE: # %bb.0: # %bb
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; P9LE-NEXT: mflr r0
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; P9LE-NEXT: .cfi_def_cfa_offset 48
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; P9LE-NEXT: .cfi_offset lr, 16
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; P9LE-NEXT: .cfi_offset r30, -16
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; P9LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
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; P9LE-NEXT: stdu r1, -48(r1)
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; P9LE-NEXT: li r3, 1
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; P9LE-NEXT: xxlxor f1, f1, f1
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; P9LE-NEXT: xxlxor f2, f2, f2
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; P9LE-NEXT: std r0, 64(r1)
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; P9LE-NEXT: rldic r30, r3, 62, 1
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; P9LE-NEXT: .p2align 5
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; P9LE-NEXT: .LBB0_1: # %bb6
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; P9LE-NEXT: #
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; P9LE-NEXT: xxlxor f3, f3, f3
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; P9LE-NEXT: xxlxor f4, f4, f4
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; P9LE-NEXT: bl __gcc_qadd
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; P9LE-NEXT: nop
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; P9LE-NEXT: addi r30, r30, -1
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; P9LE-NEXT: cmpldi r30, 0
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; P9LE-NEXT: bc 12, gt, .LBB0_1
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; P9LE-NEXT: # %bb.2: # %bb14
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; P9LE-NEXT: addi r1, r1, 48
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; P9LE-NEXT: ld r0, 16(r1)
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; P9LE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
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; P9LE-NEXT: mtlr r0
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; P9LE-NEXT: blr
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;
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; P9BE-LABEL: test_ctr0:
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; P9BE: # %bb.0: # %bb
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; P9BE-NEXT: mflr r0
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; P9BE-NEXT: stdu r1, -128(r1)
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; P9BE-NEXT: std r0, 144(r1)
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; P9BE-NEXT: .cfi_def_cfa_offset 128
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; P9BE-NEXT: .cfi_offset lr, 16
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; P9BE-NEXT: .cfi_offset r30, -16
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; P9BE-NEXT: li r3, 1
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; P9BE-NEXT: std r30, 112(r1) # 8-byte Folded Spill
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; P9BE-NEXT: xxlxor f1, f1, f1
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; P9BE-NEXT: rldic r30, r3, 62, 1
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; P9BE-NEXT: xxlxor f2, f2, f2
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; P9BE-NEXT: .p2align 5
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; P9BE-NEXT: .LBB0_1: # %bb6
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; P9BE-NEXT: #
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; P9BE-NEXT: xxlxor f3, f3, f3
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; P9BE-NEXT: xxlxor f4, f4, f4
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; P9BE-NEXT: bl __gcc_qadd
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; P9BE-NEXT: nop
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; P9BE-NEXT: addi r30, r30, -1
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; P9BE-NEXT: cmpldi r30, 0
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; P9BE-NEXT: bc 12, gt, .LBB0_1
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; P9BE-NEXT: # %bb.2: # %bb14
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; P9BE-NEXT: ld r30, 112(r1) # 8-byte Folded Reload
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; P9BE-NEXT: addi r1, r1, 128
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; P9BE-NEXT: ld r0, 16(r1)
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; P9BE-NEXT: mtlr r0
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; P9BE-NEXT: blr
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;
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; P8LE-LABEL: test_ctr0:
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; P8LE: # %bb.0: # %bb
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; P8LE-NEXT: mflr r0
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; P8LE-NEXT: .cfi_def_cfa_offset 48
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; P8LE-NEXT: .cfi_offset lr, 16
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; P8LE-NEXT: .cfi_offset r30, -16
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; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
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; P8LE-NEXT: stdu r1, -48(r1)
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; P8LE-NEXT: xxlxor f1, f1, f1
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; P8LE-NEXT: li r3, 1
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; P8LE-NEXT: std r0, 64(r1)
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; P8LE-NEXT: xxlxor f2, f2, f2
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; P8LE-NEXT: rldic r30, r3, 62, 1
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; P8LE-NEXT: .p2align 5
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; P8LE-NEXT: .LBB0_1: # %bb6
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; P8LE-NEXT: #
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; P8LE-NEXT: xxlxor f3, f3, f3
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; P8LE-NEXT: xxlxor f4, f4, f4
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; P8LE-NEXT: bl __gcc_qadd
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; P8LE-NEXT: nop
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; P8LE-NEXT: addi r30, r30, -1
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; P8LE-NEXT: cmpldi r30, 0
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; P8LE-NEXT: bc 12, gt, .LBB0_1
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; P8LE-NEXT: # %bb.2: # %bb14
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; P8LE-NEXT: addi r1, r1, 48
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; P8LE-NEXT: ld r0, 16(r1)
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; P8LE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
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; P8LE-NEXT: mtlr r0
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; P8LE-NEXT: blr
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;
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; P8BE-LABEL: test_ctr0:
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; P8BE: # %bb.0: # %bb
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; P8BE-NEXT: mflr r0
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; P8BE-NEXT: stdu r1, -128(r1)
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; P8BE-NEXT: std r0, 144(r1)
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; P8BE-NEXT: .cfi_def_cfa_offset 128
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; P8BE-NEXT: .cfi_offset lr, 16
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; P8BE-NEXT: .cfi_offset r30, -16
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; P8BE-NEXT: xxlxor f1, f1, f1
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; P8BE-NEXT: li r3, 1
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; P8BE-NEXT: std r30, 112(r1) # 8-byte Folded Spill
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; P8BE-NEXT: xxlxor f2, f2, f2
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; P8BE-NEXT: rldic r30, r3, 62, 1
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; P8BE-NEXT: .p2align 5
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; P8BE-NEXT: .LBB0_1: # %bb6
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; P8BE-NEXT: #
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; P8BE-NEXT: xxlxor f3, f3, f3
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; P8BE-NEXT: xxlxor f4, f4, f4
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; P8BE-NEXT: bl __gcc_qadd
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; P8BE-NEXT: nop
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; P8BE-NEXT: addi r30, r30, -1
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; P8BE-NEXT: cmpldi r30, 0
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; P8BE-NEXT: bc 12, gt, .LBB0_1
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; P8BE-NEXT: # %bb.2: # %bb14
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; P8BE-NEXT: ld r30, 112(r1) # 8-byte Folded Reload
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; P8BE-NEXT: addi r1, r1, 128
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; P8BE-NEXT: ld r0, 16(r1)
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; P8BE-NEXT: mtlr r0
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; P8BE-NEXT: blr
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bb:
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br label %bb6
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bb6: ; preds = %bb6, %bb
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%i = phi ppc_fp128 [ %i8, %bb6 ], [ 0xM00000000000000000000000000000000, %bb ]
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%i7 = phi i64 [ %i9, %bb6 ], [ 0, %bb ]
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%i8 = tail call ppc_fp128 @llvm.fmuladd.ppcf128(ppc_fp128 0xM00000000000000000000000000000000, ppc_fp128 0xM00000000000000000000000000000000, ppc_fp128 %i) #4
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%i9 = add i64 %i7, -4
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%i10 = icmp eq i64 %i9, 0
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br i1 %i10, label %bb14, label %bb6
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bb14: ; preds = %bb6
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ret ppc_fp128 %i8
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}
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