427fb35192
The LIT test cases were migrated with the script provided by Nikita Popov. Due to the size of the change it is split into several parts. Reviewed By: nemanja, amyk, nikic, PowerPC Differential Revision: https://reviews.llvm.org/D135470
246 lines
12 KiB
LLVM
246 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s \
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; RUN: -stop-after=finalize-isel -verify-machineinstrs | FileCheck %s
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; Verify if the mayRaiseFPException is set for FCMPD/FCMPS
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define i32 @fcmpu(double %a, double %b) {
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; CHECK-LABEL: name: fcmpu
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; CHECK: bb.0.entry:
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; CHECK-NEXT: liveins: $f1, $f2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:f8rc = COPY $f2
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:f8rc = COPY $f1
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; CHECK-NEXT: %2:crrc = nofpexcept FCMPUD [[COPY1]], [[COPY]]
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:crbitrc = COPY %2.sub_gt
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; CHECK-NEXT: [[LI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = LI8 0
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; CHECK-NEXT: [[LI8_1:%[0-9]+]]:g8rc_and_g8rc_nox0 = LI8 1
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; CHECK-NEXT: [[ISEL8_:%[0-9]+]]:g8rc = ISEL8 [[LI8_1]], [[LI8_]], [[COPY2]]
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; CHECK-NEXT: $x3 = COPY [[ISEL8_]]
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; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
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entry:
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%r = fcmp ogt double %a, %b
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%g = zext i1 %r to i32
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ret i32 %g
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}
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define double @max_typec(double %a, double %b) {
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; CHECK-LABEL: name: max_typec
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; CHECK: bb.0.entry:
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; CHECK-NEXT: liveins: $f1, $f2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vsfrc = COPY $f2
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vsfrc = COPY $f1
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; CHECK-NEXT: %2:vsfrc = nofpexcept XSMAXCDP [[COPY1]], [[COPY]]
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; CHECK-NEXT: $f1 = COPY %2
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; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $f1
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entry:
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%cmp = fcmp ogt double %a, %b
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%sel = select i1 %cmp, double %a, double %b
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ret double %sel
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}
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; Verify no mayRaiseFPException bit set on fneg & fabs
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define double @fneg(double %a) {
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; CHECK-LABEL: name: fneg
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; CHECK: bb.0.entry:
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; CHECK-NEXT: liveins: $f1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vsfrc = COPY $f1
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; CHECK-NEXT: [[XSNEGDP:%[0-9]+]]:vsfrc = XSNEGDP [[COPY]], implicit $rm
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; CHECK-NEXT: $f1 = COPY [[XSNEGDP]]
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; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $f1
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entry:
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%neg = fneg double %a
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ret double %neg
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}
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define double @fabs(double %a) {
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; CHECK-LABEL: name: fabs
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; CHECK: bb.0.entry:
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; CHECK-NEXT: liveins: $f1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vsfrc = COPY $f1
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; CHECK-NEXT: [[XSABSDP:%[0-9]+]]:vsfrc = XSABSDP [[COPY]], implicit $rm
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; CHECK-NEXT: $f1 = COPY [[XSABSDP]]
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; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $f1
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entry:
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%abs = call double @llvm.fabs.f64(double %a)
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ret double %abs
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}
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; Verify nofpexcept is set to constrained conversions when ignoring exceptions
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define void @fptoint_nofpexcept(ppc_fp128 %p, fp128 %m, ptr %addr1, ptr %addr2) {
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; CHECK-LABEL: name: fptoint_nofpexcept
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: liveins: $f1, $f2, $v2, $x7, $x8
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x8
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x7
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrrc = COPY $v2
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:f8rc = COPY $f2
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:f8rc = COPY $f1
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; CHECK-NEXT: %5:vrrc = nofpexcept XSCVQPSWZ [[COPY2]]
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:vslrc = COPY %5
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; CHECK-NEXT: [[COPY6:%[0-9]+]]:vfrc = COPY [[COPY5]].sub_64
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; CHECK-NEXT: [[MFVSRWZ:%[0-9]+]]:gprc = MFVSRWZ killed [[COPY6]]
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; CHECK-NEXT: STW killed [[MFVSRWZ]], 0, [[COPY1]] :: (volatile store (s32) into %ir.addr1)
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; CHECK-NEXT: %8:vrrc = nofpexcept XSCVQPUWZ [[COPY2]]
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; CHECK-NEXT: [[COPY7:%[0-9]+]]:vslrc = COPY %8
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; CHECK-NEXT: [[COPY8:%[0-9]+]]:vfrc = COPY [[COPY7]].sub_64
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; CHECK-NEXT: [[MFVSRWZ1:%[0-9]+]]:gprc = MFVSRWZ killed [[COPY8]]
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; CHECK-NEXT: STW killed [[MFVSRWZ1]], 0, [[COPY1]] :: (volatile store (s32) into %ir.addr1)
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; CHECK-NEXT: %11:vrrc = nofpexcept XSCVQPSDZ [[COPY2]]
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; CHECK-NEXT: %12:g8rc = nofpexcept MFVRD killed %11
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; CHECK-NEXT: STD killed %12, 0, [[COPY]] :: (volatile store (s64) into %ir.addr2)
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; CHECK-NEXT: %13:vrrc = nofpexcept XSCVQPUDZ [[COPY2]]
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; CHECK-NEXT: %14:g8rc = nofpexcept MFVRD killed %13
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; CHECK-NEXT: STD killed %14, 0, [[COPY]] :: (volatile store (s64) into %ir.addr2)
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; CHECK-NEXT: [[MFFS:%[0-9]+]]:f8rc = MFFS implicit $rm
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; CHECK-NEXT: MTFSB1 31, implicit-def $rm, implicit-def $rm
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; CHECK-NEXT: MTFSB0 30, implicit-def $rm, implicit-def $rm
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; CHECK-NEXT: %15:f8rc = nofpexcept FADD [[COPY3]], [[COPY4]], implicit $rm
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; CHECK-NEXT: MTFSFb 1, [[MFFS]], implicit-def $rm
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; CHECK-NEXT: %16:vsfrc = nofpexcept XSCVDPSXWS killed %15, implicit $rm
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; CHECK-NEXT: [[MFVSRWZ2:%[0-9]+]]:gprc = MFVSRWZ killed %16
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; CHECK-NEXT: STW killed [[MFVSRWZ2]], 0, [[COPY1]] :: (volatile store (s32) into %ir.addr1)
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; CHECK-NEXT: [[ADDIStocHA8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, %const.0
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; CHECK-NEXT: [[DFLOADf32_:%[0-9]+]]:vssrc = DFLOADf32 target-flags(ppc-toc-lo) %const.0, killed [[ADDIStocHA8_]] :: (load (s32) from constant-pool)
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; CHECK-NEXT: [[COPY9:%[0-9]+]]:f8rc = COPY [[DFLOADf32_]]
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; CHECK-NEXT: [[FCMPOD:%[0-9]+]]:crrc = FCMPOD [[COPY4]], [[COPY9]]
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; CHECK-NEXT: [[COPY10:%[0-9]+]]:crbitrc = COPY [[FCMPOD]].sub_eq
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; CHECK-NEXT: [[XXLXORdpz:%[0-9]+]]:f8rc = XXLXORdpz
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; CHECK-NEXT: [[FCMPOD1:%[0-9]+]]:crrc = FCMPOD [[COPY3]], [[XXLXORdpz]]
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; CHECK-NEXT: [[COPY11:%[0-9]+]]:crbitrc = COPY [[FCMPOD1]].sub_lt
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; CHECK-NEXT: [[CRAND:%[0-9]+]]:crbitrc = CRAND killed [[COPY10]], killed [[COPY11]]
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; CHECK-NEXT: [[COPY12:%[0-9]+]]:crbitrc = COPY [[FCMPOD]].sub_eq
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; CHECK-NEXT: [[COPY13:%[0-9]+]]:crbitrc = COPY [[FCMPOD]].sub_lt
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; CHECK-NEXT: [[CRANDC:%[0-9]+]]:crbitrc = CRANDC killed [[COPY13]], killed [[COPY12]]
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; CHECK-NEXT: [[CROR:%[0-9]+]]:crbitrc = CROR killed [[CRANDC]], killed [[CRAND]]
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; CHECK-NEXT: [[LIS:%[0-9]+]]:gprc_and_gprc_nor0 = LIS 32768
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; CHECK-NEXT: [[LI:%[0-9]+]]:gprc_and_gprc_nor0 = LI 0
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; CHECK-NEXT: [[ISEL:%[0-9]+]]:gprc = ISEL [[LI]], [[LIS]], [[CROR]]
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; CHECK-NEXT: BC [[CROR]], %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.entry:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.entry:
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; CHECK-NEXT: [[PHI:%[0-9]+]]:f8rc = PHI [[COPY9]], %bb.1, [[XXLXORdpz]], %bb.0
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; CHECK-NEXT: ADJCALLSTACKDOWN 32, 0, implicit-def dead $r1, implicit $r1
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; CHECK-NEXT: $f1 = COPY [[COPY4]]
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; CHECK-NEXT: $f2 = COPY [[COPY3]]
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; CHECK-NEXT: $f3 = COPY [[PHI]]
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; CHECK-NEXT: $f4 = COPY [[XXLXORdpz]]
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; CHECK-NEXT: BL8_NOP &__gcc_qsub, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $x2, implicit-def $r1, implicit-def $f1, implicit-def $f2
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; CHECK-NEXT: ADJCALLSTACKUP 32, 0, implicit-def dead $r1, implicit $r1
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; CHECK-NEXT: [[COPY14:%[0-9]+]]:f8rc = COPY $f1
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; CHECK-NEXT: [[COPY15:%[0-9]+]]:f8rc = COPY $f2
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; CHECK-NEXT: [[MFFS1:%[0-9]+]]:f8rc = MFFS implicit $rm
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; CHECK-NEXT: MTFSB1 31, implicit-def $rm, implicit-def $rm
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; CHECK-NEXT: MTFSB0 30, implicit-def $rm, implicit-def $rm
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; CHECK-NEXT: %37:f8rc = nofpexcept FADD [[COPY15]], [[COPY14]], implicit $rm
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; CHECK-NEXT: MTFSFb 1, [[MFFS1]], implicit-def $rm
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; CHECK-NEXT: %38:vsfrc = nofpexcept XSCVDPSXWS killed %37, implicit $rm
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; CHECK-NEXT: [[MFVSRWZ3:%[0-9]+]]:gprc = MFVSRWZ killed %38
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; CHECK-NEXT: [[XOR:%[0-9]+]]:gprc = XOR killed [[MFVSRWZ3]], killed [[ISEL]]
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; CHECK-NEXT: STW killed [[XOR]], 0, [[COPY1]] :: (volatile store (s32) into %ir.addr1)
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; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm
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entry:
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%conv1 = tail call i32 @llvm.experimental.constrained.fptosi.i32.f128(fp128 %m, metadata !"fpexcept.ignore") #0
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store volatile i32 %conv1, ptr %addr1, align 4
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%conv2 = tail call i32 @llvm.experimental.constrained.fptoui.i32.f128(fp128 %m, metadata !"fpexcept.ignore") #0
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store volatile i32 %conv2, ptr %addr1, align 4
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%conv3 = tail call i64 @llvm.experimental.constrained.fptosi.i64.f128(fp128 %m, metadata !"fpexcept.ignore") #0
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store volatile i64 %conv3, ptr %addr2, align 8
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%conv4 = tail call i64 @llvm.experimental.constrained.fptoui.i64.f128(fp128 %m, metadata !"fpexcept.ignore") #0
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store volatile i64 %conv4, ptr %addr2, align 8
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%conv5 = tail call i32 @llvm.experimental.constrained.fptosi.i32.ppcf128(ppc_fp128 %p, metadata !"fpexcept.ignore") #0
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store volatile i32 %conv5, ptr %addr1, align 4
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%conv6 = tail call i32 @llvm.experimental.constrained.fptoui.i32.ppcf128(ppc_fp128 %p, metadata !"fpexcept.ignore") #0
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store volatile i32 %conv6, ptr %addr1, align 4
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ret void
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}
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; Verify nofpexcept is NOT set to constrained conversions
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define signext i32 @q_to_i32(fp128 %m) #0 {
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; CHECK-LABEL: name: q_to_i32
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; CHECK: bb.0.entry:
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; CHECK-NEXT: liveins: $v2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vrrc = COPY $v2
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; CHECK-NEXT: [[XSCVQPSWZ:%[0-9]+]]:vrrc = XSCVQPSWZ [[COPY]]
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vslrc = COPY [[XSCVQPSWZ]]
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vfrc = COPY [[COPY1]].sub_64
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; CHECK-NEXT: [[MFVSRWZ:%[0-9]+]]:gprc = MFVSRWZ killed [[COPY2]]
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; CHECK-NEXT: [[EXTSW_32_64_:%[0-9]+]]:g8rc = EXTSW_32_64 killed [[MFVSRWZ]]
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; CHECK-NEXT: $x3 = COPY [[EXTSW_32_64_]]
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; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
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entry:
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%conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f128(fp128 %m, metadata !"fpexcept.strict") #0
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ret i32 %conv
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}
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define i64 @q_to_i64(fp128 %m) #0 {
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; CHECK-LABEL: name: q_to_i64
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; CHECK: bb.0.entry:
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; CHECK-NEXT: liveins: $v2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vrrc = COPY $v2
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; CHECK-NEXT: [[XSCVQPSDZ:%[0-9]+]]:vrrc = XSCVQPSDZ [[COPY]]
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; CHECK-NEXT: [[MFVRD:%[0-9]+]]:g8rc = MFVRD killed [[XSCVQPSDZ]]
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; CHECK-NEXT: $x3 = COPY [[MFVRD]]
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; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
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entry:
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%conv = tail call i64 @llvm.experimental.constrained.fptosi.i64.f128(fp128 %m, metadata !"fpexcept.strict") #0
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ret i64 %conv
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}
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define i64 @q_to_u64(fp128 %m) #0 {
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; CHECK-LABEL: name: q_to_u64
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; CHECK: bb.0.entry:
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; CHECK-NEXT: liveins: $v2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vrrc = COPY $v2
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; CHECK-NEXT: [[XSCVQPUDZ:%[0-9]+]]:vrrc = XSCVQPUDZ [[COPY]]
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; CHECK-NEXT: [[MFVRD:%[0-9]+]]:g8rc = MFVRD killed [[XSCVQPUDZ]]
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; CHECK-NEXT: $x3 = COPY [[MFVRD]]
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; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
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entry:
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%conv = tail call i64 @llvm.experimental.constrained.fptoui.i64.f128(fp128 %m, metadata !"fpexcept.strict") #0
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ret i64 %conv
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}
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define zeroext i32 @q_to_u32(fp128 %m) #0 {
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; CHECK-LABEL: name: q_to_u32
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; CHECK: bb.0.entry:
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; CHECK-NEXT: liveins: $v2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vrrc = COPY $v2
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; CHECK-NEXT: [[XSCVQPUWZ:%[0-9]+]]:vrrc = XSCVQPUWZ [[COPY]]
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vslrc = COPY [[XSCVQPUWZ]]
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vfrc = COPY [[COPY1]].sub_64
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; CHECK-NEXT: [[MFVSRWZ:%[0-9]+]]:gprc = MFVSRWZ killed [[COPY2]]
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; CHECK-NEXT: [[DEF:%[0-9]+]]:g8rc = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF]], killed [[MFVSRWZ]], %subreg.sub_32
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; CHECK-NEXT: [[RLDICL:%[0-9]+]]:g8rc = RLDICL killed [[INSERT_SUBREG]], 0, 32
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; CHECK-NEXT: $x3 = COPY [[RLDICL]]
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; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
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entry:
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%conv = tail call i32 @llvm.experimental.constrained.fptoui.i32.f128(fp128 %m, metadata !"fpexcept.strict") #0
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ret i32 %conv
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}
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declare double @llvm.fabs.f64(double)
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declare i32 @llvm.experimental.constrained.fptosi.i32.f128(fp128, metadata)
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declare i64 @llvm.experimental.constrained.fptosi.i64.f128(fp128, metadata)
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declare i64 @llvm.experimental.constrained.fptoui.i64.f128(fp128, metadata)
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declare i32 @llvm.experimental.constrained.fptoui.i32.f128(fp128, metadata)
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declare i32 @llvm.experimental.constrained.fptosi.i32.ppcf128(ppc_fp128, metadata)
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declare i32 @llvm.experimental.constrained.fptoui.i32.ppcf128(ppc_fp128, metadata)
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attributes #0 = { strictfp }
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