5403c59c60
The LIT test cases were migrated with the script provided by Nikita Popov. Due to the size of the change it is split into several parts. Reviewed By: nemanja, nikic Differential Revision: https://reviews.llvm.org/D135474
115 lines
3.5 KiB
LLVM
115 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr7 %s -o - | FileCheck %s --check-prefix=PWR7
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr9 %s -o - | FileCheck %s --check-prefix=PWR9
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@value8 = dso_local global { i8 } zeroinitializer, align 1
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@value16 = dso_local global { i16 } zeroinitializer, align 2
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@global_int = dso_local local_unnamed_addr global i32 0, align 4
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define dso_local zeroext i32 @testI8(i8 zeroext %val) local_unnamed_addr #0 {
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; PWR7-LABEL: testI8:
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; PWR7: # %bb.0: # %entry
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; PWR7-NEXT: addis 4, 2, value8@toc@ha
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; PWR7-NEXT: li 6, 255
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; PWR7-NEXT: sync
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; PWR7-NEXT: addi 5, 4, value8@toc@l
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; PWR7-NEXT: rlwinm 4, 5, 3, 27, 28
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; PWR7-NEXT: rldicr 5, 5, 0, 61
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; PWR7-NEXT: xori 4, 4, 24
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; PWR7-NEXT: slw 7, 3, 4
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; PWR7-NEXT: slw 3, 6, 4
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; PWR7-NEXT: and 6, 7, 3
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; PWR7-NEXT: .LBB0_1: # %entry
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; PWR7-NEXT: #
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; PWR7-NEXT: lwarx 7, 0, 5
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; PWR7-NEXT: andc 8, 7, 3
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; PWR7-NEXT: or 8, 6, 8
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; PWR7-NEXT: stwcx. 8, 0, 5
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; PWR7-NEXT: bne 0, .LBB0_1
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; PWR7-NEXT: # %bb.2: # %entry
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; PWR7-NEXT: srw 3, 7, 4
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; PWR7-NEXT: addis 5, 2, global_int@toc@ha
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; PWR7-NEXT: lwsync
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; PWR7-NEXT: clrlwi 4, 3, 24
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; PWR7-NEXT: li 3, 55
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; PWR7-NEXT: stw 4, global_int@toc@l(5)
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; PWR7-NEXT: blr
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;
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; PWR9-LABEL: testI8:
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; PWR9: # %bb.0: # %entry
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; PWR9-NEXT: addis 4, 2, value8@toc@ha
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; PWR9-NEXT: sync
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; PWR9-NEXT: addi 5, 4, value8@toc@l
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; PWR9-NEXT: .LBB0_1: # %entry
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; PWR9-NEXT: #
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; PWR9-NEXT: lbarx 4, 0, 5
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; PWR9-NEXT: stbcx. 3, 0, 5
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; PWR9-NEXT: bne 0, .LBB0_1
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; PWR9-NEXT: # %bb.2: # %entry
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; PWR9-NEXT: addis 3, 2, global_int@toc@ha
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; PWR9-NEXT: lwsync
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; PWR9-NEXT: stw 4, global_int@toc@l(3)
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; PWR9-NEXT: li 3, 55
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; PWR9-NEXT: blr
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entry:
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%0 = atomicrmw xchg ptr @value8, i8 %val seq_cst, align 1
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%conv = zext i8 %0 to i32
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store i32 %conv, ptr @global_int, align 4
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ret i32 55
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}
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define dso_local zeroext i32 @testI16(i16 zeroext %val) local_unnamed_addr #0 {
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; PWR7-LABEL: testI16:
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; PWR7: # %bb.0: # %entry
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; PWR7-NEXT: addis 4, 2, value16@toc@ha
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; PWR7-NEXT: li 6, 0
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; PWR7-NEXT: sync
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; PWR7-NEXT: addi 5, 4, value16@toc@l
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; PWR7-NEXT: ori 6, 6, 65535
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; PWR7-NEXT: rlwinm 4, 5, 3, 27, 27
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; PWR7-NEXT: rldicr 5, 5, 0, 61
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; PWR7-NEXT: xori 4, 4, 16
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; PWR7-NEXT: slw 7, 3, 4
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; PWR7-NEXT: slw 3, 6, 4
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; PWR7-NEXT: and 6, 7, 3
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; PWR7-NEXT: .LBB1_1: # %entry
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; PWR7-NEXT: #
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; PWR7-NEXT: lwarx 7, 0, 5
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; PWR7-NEXT: andc 8, 7, 3
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; PWR7-NEXT: or 8, 6, 8
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; PWR7-NEXT: stwcx. 8, 0, 5
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; PWR7-NEXT: bne 0, .LBB1_1
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; PWR7-NEXT: # %bb.2: # %entry
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; PWR7-NEXT: srw 3, 7, 4
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; PWR7-NEXT: addis 5, 2, global_int@toc@ha
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; PWR7-NEXT: lwsync
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; PWR7-NEXT: clrlwi 4, 3, 16
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; PWR7-NEXT: li 3, 55
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; PWR7-NEXT: stw 4, global_int@toc@l(5)
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; PWR7-NEXT: blr
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;
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; PWR9-LABEL: testI16:
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; PWR9: # %bb.0: # %entry
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; PWR9-NEXT: addis 4, 2, value16@toc@ha
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; PWR9-NEXT: sync
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; PWR9-NEXT: addi 5, 4, value16@toc@l
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; PWR9-NEXT: .LBB1_1: # %entry
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; PWR9-NEXT: #
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; PWR9-NEXT: lharx 4, 0, 5
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; PWR9-NEXT: sthcx. 3, 0, 5
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; PWR9-NEXT: bne 0, .LBB1_1
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; PWR9-NEXT: # %bb.2: # %entry
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; PWR9-NEXT: addis 3, 2, global_int@toc@ha
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; PWR9-NEXT: lwsync
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; PWR9-NEXT: stw 4, global_int@toc@l(3)
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; PWR9-NEXT: li 3, 55
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; PWR9-NEXT: blr
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entry:
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%0 = atomicrmw xchg ptr @value16, i16 %val seq_cst, align 2
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%conv = zext i16 %0 to i32
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store i32 %conv, ptr @global_int, align 4
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ret i32 55
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}
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attributes #0 = { nounwind }
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