b5e1fc19da
We added a new post-isel CTRLoop pass in D122125. That pass will expand the hardware loop related intrinsic to CTR loop or normal loop based on the loop context. So we don't need to conservatively check the CTR clobber now on the IR level. Reviewed By: lkail Differential Revision: https://reviews.llvm.org/D135847
314 lines
9.6 KiB
LLVM
314 lines
9.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
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; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
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; RUN: -check-prefix=CHECK-P9
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define void @julia__typed_vcat_20() #0 {
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; CHECK-LABEL: julia__typed_vcat_20:
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; CHECK: # %bb.0: # %bb
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
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; CHECK-NEXT: stdu r1, -48(r1)
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; CHECK-NEXT: li r30, 0
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; CHECK-NEXT: li r3, 1
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; CHECK-NEXT: std r0, 64(r1)
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB0_1: # %bb3
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; CHECK-NEXT: #
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; CHECK-NEXT: addi r3, r3, -1
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; CHECK-NEXT: mtfprd f0, r3
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; CHECK-NEXT: xscvsxdsp f1, f0
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; CHECK-NEXT: bl __gnu_f2h_ieee
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; CHECK-NEXT: nop
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; CHECK-NEXT: clrldi r3, r3, 48
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; CHECK-NEXT: bl __gnu_h2f_ieee
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi r30, r30, -1
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; CHECK-NEXT: li r3, 0
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; CHECK-NEXT: cmpldi r30, 0
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; CHECK-NEXT: bc 12, gt, .LBB0_1
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; CHECK-NEXT: # %bb.2: # %bb11
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; CHECK-NEXT: bl __gnu_f2h_ieee
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; CHECK-NEXT: nop
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; CHECK-NEXT: sth r3, 0(r3)
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;
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; CHECK-P9-LABEL: julia__typed_vcat_20:
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; CHECK-P9: # %bb.0: # %bb
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; CHECK-P9-NEXT: li r3, 0
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; CHECK-P9-NEXT: mtctr r3
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; CHECK-P9-NEXT: li r3, 1
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; CHECK-P9-NEXT: .p2align 4
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; CHECK-P9-NEXT: .LBB0_1: # %bb3
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; CHECK-P9-NEXT: #
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; CHECK-P9-NEXT: addi r3, r3, -1
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; CHECK-P9-NEXT: mtfprd f0, r3
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; CHECK-P9-NEXT: xscvsxdsp f0, f0
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; CHECK-P9-NEXT: xscvdphp f0, f0
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; CHECK-P9-NEXT: mffprwz r3, f0
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; CHECK-P9-NEXT: clrlwi r3, r3, 16
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; CHECK-P9-NEXT: mtfprwz f0, r3
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; CHECK-P9-NEXT: li r3, 0
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; CHECK-P9-NEXT: xscvhpdp f0, f0
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; CHECK-P9-NEXT: bdnz .LBB0_1
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; CHECK-P9-NEXT: # %bb.2: # %bb11
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; CHECK-P9-NEXT: xscvdphp f0, f0
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; CHECK-P9-NEXT: stxsihx f0, 0, r3
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bb:
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%i = load i64, ptr addrspace(11) null, align 8
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%i1 = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %i, i64 0)
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%i2 = extractvalue { i64, i1 } %i1, 0
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br label %bb3
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bb3: ; preds = %bb3, %bb
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%i4 = phi i64 [ %i10, %bb3 ], [ 1, %bb ]
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%i5 = phi i64 [ 0, %bb3 ], [ 1, %bb ]
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%i6 = add nsw i64 %i5, -1
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%i7 = add i64 %i6, 0
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%i8 = sitofp i64 %i7 to half
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store half %i8, ptr addrspace(13) undef, align 2
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%i9 = icmp eq i64 %i4, 0
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%i10 = add i64 %i4, 1
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br i1 %i9, label %bb11, label %bb3
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bb11: ; preds = %bb3
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unreachable
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}
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declare { i64, i1 } @llvm.ssub.with.overflow.i64(i64, i64) #0
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define void @julia__hypot_17() #0 {
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; CHECK-LABEL: julia__hypot_17:
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; CHECK: # %bb.0: # %bb
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
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; CHECK-NEXT: stdu r1, -48(r1)
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; CHECK-NEXT: li r30, 3
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; CHECK-NEXT: std r0, 64(r1)
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; CHECK-NEXT: .p2align 5
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; CHECK-NEXT: .LBB1_1: # %bb1
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; CHECK-NEXT: #
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; CHECK-NEXT: addi r30, r30, -1
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; CHECK-NEXT: cmpldi r30, 0
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; CHECK-NEXT: bc 4, gt, .LBB1_3
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; CHECK-NEXT: # %bb.2: # %bb3
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; CHECK-NEXT: #
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; CHECK-NEXT: lhz r3, 0(0)
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; CHECK-NEXT: bl __gnu_h2f_ieee
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; CHECK-NEXT: nop
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; CHECK-NEXT: fcmpu cr0, f1, f1
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; CHECK-NEXT: bun cr0, .LBB1_1
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; CHECK-NEXT: .LBB1_3: # %bb9
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; CHECK-NEXT: addi r1, r1, 48
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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;
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; CHECK-P9-LABEL: julia__hypot_17:
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; CHECK-P9: # %bb.0: # %bb
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; CHECK-P9-NEXT: li r3, 3
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; CHECK-P9-NEXT: mtctr r3
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; CHECK-P9-NEXT: li r3, 0
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; CHECK-P9-NEXT: .p2align 5
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; CHECK-P9-NEXT: .LBB1_1: # %bb1
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; CHECK-P9-NEXT: #
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; CHECK-P9-NEXT: bdzlr
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; CHECK-P9-NEXT: # %bb.2: # %bb3
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; CHECK-P9-NEXT: #
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; CHECK-P9-NEXT: lxsihzx f0, 0, r3
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; CHECK-P9-NEXT: xscvhpdp f0, f0
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; CHECK-P9-NEXT: fcmpu cr0, f0, f0
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; CHECK-P9-NEXT: bun cr0, .LBB1_1
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; CHECK-P9-NEXT: # %bb.3: # %bb9
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; CHECK-P9-NEXT: blr
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bb:
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br label %bb1
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bb1: ; preds = %bb3, %bb
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%i = phi i64 [ %i4, %bb3 ], [ 2, %bb ]
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%i2 = icmp eq i64 %i, 4
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br i1 %i2, label %bb9, label %bb3
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bb3: ; preds = %bb1
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%i4 = add nuw nsw i64 %i, 1
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%i5 = load half, ptr null, align 2
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%i6 = fpext half %i5 to float
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%i7 = fcmp uno float %i6, 0.000000e+00
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%i8 = or i1 %i7, false
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br i1 %i8, label %bb1, label %bb9
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bb9: ; preds = %bb3, %bb1
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ret void
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}
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define void @func_48786() #0 {
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; CHECK-LABEL: func_48786:
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; CHECK: # %bb.0: # %bb
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; CHECK-NEXT: mfocrf r12, 32
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stw r12, 8(r1)
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; CHECK-NEXT: stdu r1, -48(r1)
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; CHECK-NEXT: std r0, 64(r1)
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; CHECK-NEXT: std r30, 32(r1) # 8-byte Folded Spill
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; CHECK-NEXT: # implicit-def: $x30
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; CHECK-NEXT: ld r3, 0(r3)
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; CHECK-NEXT: cmpdi r3, 0
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; CHECK-NEXT: crnot 4*cr2+lt, eq
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; CHECK-NEXT: b .LBB2_2
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB2_1: # %bb10
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; CHECK-NEXT: #
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; CHECK-NEXT: addi r30, r30, -1
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; CHECK-NEXT: cmpldi r30, 0
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; CHECK-NEXT: bc 4, gt, .LBB2_5
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; CHECK-NEXT: .LBB2_2: # %bb2
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; CHECK-NEXT: #
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; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB2_1
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; CHECK-NEXT: # %bb.3: # %bb4
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; CHECK-NEXT: #
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; CHECK-NEXT: lhz r3, 0(r3)
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; CHECK-NEXT: bl __gnu_h2f_ieee
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; CHECK-NEXT: nop
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; CHECK-NEXT: bc 4, 4*cr2+lt, .LBB2_6
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; CHECK-NEXT: # %bb.4: # %bb8
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; CHECK-NEXT: #
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; CHECK-NEXT: bl __gnu_f2h_ieee
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; CHECK-NEXT: nop
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; CHECK-NEXT: sth r3, 0(0)
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; CHECK-NEXT: b .LBB2_1
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; CHECK-NEXT: .LBB2_5: # %bb14
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; CHECK-NEXT: ld r30, 32(r1) # 8-byte Folded Reload
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; CHECK-NEXT: addi r1, r1, 48
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: lwz r12, 8(r1)
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; CHECK-NEXT: mtocrf 32, r12
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB2_6: # %bb15
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;
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; CHECK-P9-LABEL: func_48786:
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; CHECK-P9: # %bb.0: # %bb
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; CHECK-P9-NEXT: ld r3, 0(r3)
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; CHECK-P9-NEXT: cmpdi r3, 0
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; CHECK-P9-NEXT: mtctr r3
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; CHECK-P9-NEXT: li r3, 0
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; CHECK-P9-NEXT: crnot 4*cr5+lt, eq
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; CHECK-P9-NEXT: b .LBB2_2
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; CHECK-P9-NEXT: .p2align 5
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; CHECK-P9-NEXT: .LBB2_1: # %bb10
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; CHECK-P9-NEXT: #
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; CHECK-P9-NEXT: bdzlr
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; CHECK-P9-NEXT: .LBB2_2: # %bb2
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; CHECK-P9-NEXT: #
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; CHECK-P9-NEXT: bc 12, 4*cr5+lt, .LBB2_1
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; CHECK-P9-NEXT: # %bb.3: # %bb4
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; CHECK-P9-NEXT: #
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; CHECK-P9-NEXT: lxsihzx f0, 0, r3
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; CHECK-P9-NEXT: xscvhpdp f0, f0
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; CHECK-P9-NEXT: bc 4, 4*cr5+lt, .LBB2_5
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; CHECK-P9-NEXT: # %bb.4: # %bb8
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; CHECK-P9-NEXT: #
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; CHECK-P9-NEXT: xscvdphp f0, f0
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; CHECK-P9-NEXT: stxsihx f0, 0, r3
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; CHECK-P9-NEXT: b .LBB2_1
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; CHECK-P9-NEXT: .LBB2_5: # %bb15
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bb:
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%i = load i64, ptr addrspace(11) undef, align 8
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%i1 = load i64, ptr addrspace(11) undef, align 8
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br label %bb2
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bb2: ; preds = %bb12, %bb
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%i3 = phi i64 [ undef, %bb ], [ %i13, %bb12 ]
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br i1 undef, label %bb10, label %bb4
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bb4: ; preds = %bb2
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switch i32 undef, label %bb9 [
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i32 1426063360, label %bb5
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i32 1275068416, label %bb5
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]
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bb5: ; preds = %bb4, %bb4
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%i6 = load half, ptr addrspace(13) undef, align 2
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%i7 = icmp ult i64 0, %i1
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br i1 %i7, label %bb8, label %bb15
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bb8: ; preds = %bb5
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store half %i6, ptr addrspace(13) null, align 2
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br label %bb10
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bb9: ; preds = %bb4
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unreachable
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bb10: ; preds = %bb8, %bb2
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%i11 = icmp eq i64 %i3, 0
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br i1 %i11, label %bb14, label %bb12
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bb12: ; preds = %bb10
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%i13 = add i64 %i3, 1
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br label %bb2
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bb14: ; preds = %bb10
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ret void
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bb15: ; preds = %bb5
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unreachable
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}
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define void @func_48785(half %arg) #0 {
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; CHECK-LABEL: func_48785:
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; CHECK: # %bb.0: # %bb
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: std r29, -32(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r30, -24(r1) # 8-byte Folded Spill
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; CHECK-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill
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; CHECK-NEXT: stdu r1, -64(r1)
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; CHECK-NEXT: fmr f31, f1
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; CHECK-NEXT: li r3, 1
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; CHECK-NEXT: li r29, 0
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; CHECK-NEXT: std r0, 80(r1)
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; CHECK-NEXT: rldic r30, r3, 62, 1
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; CHECK-NEXT: .p2align 5
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; CHECK-NEXT: .LBB3_1: # %bb1
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; CHECK-NEXT: #
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; CHECK-NEXT: fmr f1, f31
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; CHECK-NEXT: bl __gnu_f2h_ieee
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi r30, r30, -1
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; CHECK-NEXT: sth r3, 0(r29)
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; CHECK-NEXT: addi r29, r29, 24
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; CHECK-NEXT: cmpldi r30, 0
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; CHECK-NEXT: bc 12, gt, .LBB3_1
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; CHECK-NEXT: # %bb.2: # %bb5
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;
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; CHECK-P9-LABEL: func_48785:
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; CHECK-P9: # %bb.0: # %bb
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; CHECK-P9-NEXT: li r3, 1
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; CHECK-P9-NEXT: rldic r3, r3, 62, 1
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; CHECK-P9-NEXT: mtctr r3
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; CHECK-P9-NEXT: li r3, 0
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; CHECK-P9-NEXT: .p2align 4
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; CHECK-P9-NEXT: .LBB3_1: # %bb1
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; CHECK-P9-NEXT: #
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; CHECK-P9-NEXT: xscvdphp f0, f1
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; CHECK-P9-NEXT: stxsihx f0, 0, r3
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; CHECK-P9-NEXT: addi r3, r3, 24
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; CHECK-P9-NEXT: bdnz .LBB3_1
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; CHECK-P9-NEXT: # %bb.2: # %bb5
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bb:
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br label %bb1
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bb1: ; preds = %bb1, %bb
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%i = phi i64 [ 0, %bb ], [ %i3, %bb1 ]
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%i2 = getelementptr inbounds half, ptr addrspace(13) null, i64 %i
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store half %arg, ptr addrspace(13) %i2, align 2
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%i3 = add i64 %i, 12
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%i4 = icmp eq i64 %i3, 0
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br i1 %i4, label %bb5, label %bb1
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bb5: ; preds = %bb1
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unreachable
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}
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attributes #0 = { nounwind }
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