335e8bf100
This patch changes the PowerPC backend to generate VSX load/store instructions for all vector loads/stores on Power8 and earlier (LE) instead of VMX load/store instructions. The reason for this change is because VMX instructions require the vector to be 16-byte aligned. So, a vector load/store will fail with VMX instructions if the vector is misaligned. Also, `gcc` generates VSX instructions in this situation which allow for unaligned access but require a swap instruction after loading/before storing. This is not an issue for BE because we already emit VSX instructions since no swap is required. And this is not an issue on Power9 and up since we have access to `lxv[x]`/`stxv[x]` which allow for unaligned access and do not require swaps. This patch also delays the VSX load/store for LE combines until after LegalizeOps to prioritize other load/store combines. Reviewed By: #powerpc, stefanp Differential Revision: https://reviews.llvm.org/D127309
294 lines
7.6 KiB
LLVM
294 lines
7.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=powerpc64le-- | FileCheck %s
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; If positive...
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define i32 @zext_ifpos(i32 %x) {
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; CHECK-LABEL: zext_ifpos:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31
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; CHECK-NEXT: xori 3, 3, 1
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; CHECK-NEXT: blr
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%c = icmp sgt i32 %x, -1
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%e = zext i1 %c to i32
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ret i32 %e
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}
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define i32 @add_zext_ifpos(i32 %x) {
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; CHECK-LABEL: add_zext_ifpos:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srawi 3, 3, 31
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; CHECK-NEXT: addi 3, 3, 42
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; CHECK-NEXT: blr
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%c = icmp sgt i32 %x, -1
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%e = zext i1 %c to i32
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%r = add i32 %e, 41
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ret i32 %r
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}
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define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {
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; CHECK-LABEL: add_zext_ifpos_vec_splat:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xxleqv 35, 35, 35
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; CHECK-NEXT: addis 3, 2, .LCPI2_0@toc@ha
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; CHECK-NEXT: addi 3, 3, .LCPI2_0@toc@l
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; CHECK-NEXT: vcmpgtsw 2, 2, 3
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; CHECK-NEXT: lxvd2x 0, 0, 3
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; CHECK-NEXT: xxswapd 35, 0
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; CHECK-NEXT: vsubuwm 2, 3, 2
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; CHECK-NEXT: blr
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%c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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%e = zext <4 x i1> %c to <4 x i32>
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%r = add <4 x i32> %e, <i32 41, i32 41, i32 41, i32 41>
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ret <4 x i32> %r
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}
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define i32 @sel_ifpos_tval_bigger(i32 %x) {
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; CHECK-LABEL: sel_ifpos_tval_bigger:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31
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; CHECK-NEXT: xori 3, 3, 1
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; CHECK-NEXT: addi 3, 3, 41
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; CHECK-NEXT: blr
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%c = icmp sgt i32 %x, -1
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%r = select i1 %c, i32 42, i32 41
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ret i32 %r
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}
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define i32 @sext_ifpos(i32 %x) {
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; CHECK-LABEL: sext_ifpos:
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; CHECK: # %bb.0:
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; CHECK-NEXT: not 3, 3
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; CHECK-NEXT: srawi 3, 3, 31
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; CHECK-NEXT: blr
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%c = icmp sgt i32 %x, -1
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%e = sext i1 %c to i32
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ret i32 %e
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}
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define i32 @add_sext_ifpos(i32 %x) {
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; CHECK-LABEL: add_sext_ifpos:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srwi 3, 3, 31
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; CHECK-NEXT: addi 3, 3, 41
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; CHECK-NEXT: blr
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%c = icmp sgt i32 %x, -1
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%e = sext i1 %c to i32
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%r = add i32 %e, 42
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ret i32 %r
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}
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define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {
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; CHECK-LABEL: add_sext_ifpos_vec_splat:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xxleqv 35, 35, 35
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; CHECK-NEXT: addis 3, 2, .LCPI6_0@toc@ha
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; CHECK-NEXT: addi 3, 3, .LCPI6_0@toc@l
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; CHECK-NEXT: vcmpgtsw 2, 2, 3
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; CHECK-NEXT: lxvd2x 0, 0, 3
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; CHECK-NEXT: xxswapd 35, 0
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; CHECK-NEXT: vadduwm 2, 2, 3
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; CHECK-NEXT: blr
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%c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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%e = sext <4 x i1> %c to <4 x i32>
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%r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
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ret <4 x i32> %r
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}
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define i32 @sel_ifpos_fval_bigger(i32 %x) {
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; CHECK-LABEL: sel_ifpos_fval_bigger:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31
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; CHECK-NEXT: xori 3, 3, 1
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; CHECK-NEXT: subfic 3, 3, 42
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; CHECK-NEXT: blr
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%c = icmp sgt i32 %x, -1
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%r = select i1 %c, i32 41, i32 42
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ret i32 %r
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}
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; If negative...
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define i32 @zext_ifneg(i32 %x) {
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; CHECK-LABEL: zext_ifneg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31
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; CHECK-NEXT: blr
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%c = icmp slt i32 %x, 0
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%r = zext i1 %c to i32
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ret i32 %r
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}
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define i32 @add_zext_ifneg(i32 %x) {
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; CHECK-LABEL: add_zext_ifneg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srwi 3, 3, 31
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; CHECK-NEXT: addi 3, 3, 41
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; CHECK-NEXT: blr
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%c = icmp slt i32 %x, 0
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%e = zext i1 %c to i32
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%r = add i32 %e, 41
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ret i32 %r
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}
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define i32 @sel_ifneg_tval_bigger(i32 %x) {
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; CHECK-LABEL: sel_ifneg_tval_bigger:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31
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; CHECK-NEXT: addi 3, 3, 41
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; CHECK-NEXT: blr
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%c = icmp slt i32 %x, 0
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%r = select i1 %c, i32 42, i32 41
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ret i32 %r
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}
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define i32 @sext_ifneg(i32 %x) {
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; CHECK-LABEL: sext_ifneg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srawi 3, 3, 31
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; CHECK-NEXT: blr
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%c = icmp slt i32 %x, 0
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%r = sext i1 %c to i32
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ret i32 %r
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}
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define i32 @add_sext_ifneg(i32 %x) {
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; CHECK-LABEL: add_sext_ifneg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srawi 3, 3, 31
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; CHECK-NEXT: addi 3, 3, 42
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; CHECK-NEXT: blr
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%c = icmp slt i32 %x, 0
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%e = sext i1 %c to i32
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%r = add i32 %e, 42
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ret i32 %r
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}
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define i32 @sel_ifneg_fval_bigger(i32 %x) {
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; CHECK-LABEL: sel_ifneg_fval_bigger:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31
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; CHECK-NEXT: subfic 3, 3, 42
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; CHECK-NEXT: blr
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%c = icmp slt i32 %x, 0
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%r = select i1 %c, i32 41, i32 42
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ret i32 %r
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}
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define i32 @add_lshr_not(i32 %x) {
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; CHECK-LABEL: add_lshr_not:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srawi 3, 3, 31
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; CHECK-NEXT: addi 3, 3, 42
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; CHECK-NEXT: blr
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%not = xor i32 %x, -1
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%sh = lshr i32 %not, 31
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%r = add i32 %sh, 41
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ret i32 %r
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}
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define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) {
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; CHECK-LABEL: add_lshr_not_vec_splat:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vspltisw 3, -16
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; CHECK-NEXT: vspltisw 4, 15
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; CHECK-NEXT: addis 3, 2, .LCPI15_0@toc@ha
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; CHECK-NEXT: addi 3, 3, .LCPI15_0@toc@l
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; CHECK-NEXT: lxvd2x 0, 0, 3
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; CHECK-NEXT: vsubuwm 3, 4, 3
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; CHECK-NEXT: vsraw 2, 2, 3
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; CHECK-NEXT: xxswapd 35, 0
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; CHECK-NEXT: vadduwm 2, 2, 3
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; CHECK-NEXT: blr
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%c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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%e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
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%r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
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ret <4 x i32> %r
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}
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define i32 @sub_lshr_not(i32 %x) {
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; CHECK-LABEL: sub_lshr_not:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srwi 3, 3, 31
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; CHECK-NEXT: ori 3, 3, 42
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; CHECK-NEXT: blr
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%not = xor i32 %x, -1
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%sh = lshr i32 %not, 31
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%r = sub i32 43, %sh
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ret i32 %r
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}
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define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {
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; CHECK-LABEL: sub_lshr_not_vec_splat:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vspltisw 3, -16
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; CHECK-NEXT: vspltisw 4, 15
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; CHECK-NEXT: addis 3, 2, .LCPI17_0@toc@ha
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; CHECK-NEXT: addi 3, 3, .LCPI17_0@toc@l
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; CHECK-NEXT: lxvd2x 0, 0, 3
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; CHECK-NEXT: vsubuwm 3, 4, 3
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; CHECK-NEXT: vsrw 2, 2, 3
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; CHECK-NEXT: xxswapd 35, 0
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; CHECK-NEXT: vadduwm 2, 2, 3
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; CHECK-NEXT: blr
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%c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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%e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
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%r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
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ret <4 x i32> %r
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}
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define i32 @sub_lshr(i32 %x, i32 %y) {
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; CHECK-LABEL: sub_lshr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srawi 3, 3, 31
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; CHECK-NEXT: add 3, 4, 3
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; CHECK-NEXT: blr
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%sh = lshr i32 %x, 31
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%r = sub i32 %y, %sh
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ret i32 %r
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}
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define <4 x i32> @sub_lshr_vec(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: sub_lshr_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vspltisw 4, -16
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; CHECK-NEXT: vspltisw 5, 15
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; CHECK-NEXT: vsubuwm 4, 5, 4
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; CHECK-NEXT: vsraw 2, 2, 4
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; CHECK-NEXT: vadduwm 2, 3, 2
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; CHECK-NEXT: blr
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%sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
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%r = sub <4 x i32> %y, %sh
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ret <4 x i32> %r
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}
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define i32 @sub_const_op_lshr(i32 %x) {
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; CHECK-LABEL: sub_const_op_lshr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srawi 3, 3, 31
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; CHECK-NEXT: addi 3, 3, 43
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; CHECK-NEXT: blr
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%sh = lshr i32 %x, 31
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%r = sub i32 43, %sh
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ret i32 %r
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}
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define <4 x i32> @sub_const_op_lshr_vec(<4 x i32> %x) {
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; CHECK-LABEL: sub_const_op_lshr_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vspltisw 3, -16
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; CHECK-NEXT: vspltisw 4, 15
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; CHECK-NEXT: addis 3, 2, .LCPI21_0@toc@ha
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; CHECK-NEXT: addi 3, 3, .LCPI21_0@toc@l
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; CHECK-NEXT: lxvd2x 0, 0, 3
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; CHECK-NEXT: vsubuwm 3, 4, 3
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; CHECK-NEXT: vsraw 2, 2, 3
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; CHECK-NEXT: xxswapd 35, 0
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; CHECK-NEXT: vadduwm 2, 2, 3
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; CHECK-NEXT: blr
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%sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
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%r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %sh
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ret <4 x i32> %r
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}
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