5403c59c60
The LIT test cases were migrated with the script provided by Nikita Popov. Due to the size of the change it is split into several parts. Reviewed By: nemanja, nikic Differential Revision: https://reviews.llvm.org/D135474
110 lines
3.4 KiB
LLVM
110 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le < %s | FileCheck %s
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define i64 @test1(ptr %a, ptr %b) {
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; CHECK-LABEL: test1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mr 5, 3
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; CHECK-NEXT: ld 3, 0(3)
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; CHECK-NEXT: ld 4, 0(4)
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; CHECK-NEXT: mtvsrd 34, 3
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; CHECK-NEXT: add 3, 3, 4
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; CHECK-NEXT: mtvsrd 35, 4
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; CHECK-NEXT: vavgsb 2, 2, 3
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; CHECK-NEXT: stxsdx 34, 0, 5
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; CHECK-NEXT: blr
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entry:
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%lhs = load i64, ptr %a, align 8
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%rhs = load i64, ptr %b, align 8
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%sum = add i64 %lhs, %rhs
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%lv = insertelement <2 x i64> undef, i64 %lhs, i32 0
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%rv = insertelement <2 x i64> undef, i64 %rhs, i32 0
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%lhc = bitcast <2 x i64> %lv to <16 x i8>
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%rhc = bitcast <2 x i64> %rv to <16 x i8>
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%add = call <16 x i8> @llvm.ppc.altivec.vavgsb(<16 x i8> %lhc, <16 x i8> %rhc)
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%cb = bitcast <16 x i8> %add to <2 x i64>
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%fv = extractelement <2 x i64> %cb, i32 0
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store i64 %fv, ptr %a, align 8
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ret i64 %sum
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}
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define i64 @test2(ptr %a, ptr %b) {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mr 5, 3
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; CHECK-NEXT: ld 3, 0(3)
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; CHECK-NEXT: ld 4, 0(4)
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; CHECK-NEXT: mtvsrd 34, 3
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; CHECK-NEXT: add 3, 3, 4
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; CHECK-NEXT: mtvsrd 35, 4
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; CHECK-NEXT: vadduhm 2, 2, 3
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; CHECK-NEXT: stxsdx 34, 0, 5
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; CHECK-NEXT: blr
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entry:
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%lhs = load i64, ptr %a, align 8
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%rhs = load i64, ptr %b, align 8
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%sum = add i64 %lhs, %rhs
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%lv = insertelement <2 x i64> undef, i64 %lhs, i32 0
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%rv = insertelement <2 x i64> undef, i64 %rhs, i32 0
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%lhc = bitcast <2 x i64> %lv to <8 x i16>
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%rhc = bitcast <2 x i64> %rv to <8 x i16>
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%add = add <8 x i16> %lhc, %rhc
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%cb = bitcast <8 x i16> %add to <2 x i64>
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%fv = extractelement <2 x i64> %cb, i32 0
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store i64 %fv, ptr %a, align 8
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ret i64 %sum
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}
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; Ensure that vec-ops with multiple uses aren't simplified.
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define signext i16 @vecop_uses(ptr %addr) {
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; CHECK-LABEL: vecop_uses:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 4, 16
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; CHECK-NEXT: lxvd2x 1, 0, 3
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; CHECK-NEXT: lxvd2x 0, 3, 4
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; CHECK-NEXT: xxswapd 35, 1
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; CHECK-NEXT: xxswapd 34, 0
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; CHECK-NEXT: vminsh 2, 3, 2
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; CHECK-NEXT: xxswapd 35, 34
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; CHECK-NEXT: vminsh 2, 2, 3
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; CHECK-NEXT: xxspltw 35, 34, 2
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; CHECK-NEXT: vminsh 2, 2, 3
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; CHECK-NEXT: vsplth 3, 2, 6
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; CHECK-NEXT: vminsh 2, 2, 3
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; CHECK-NEXT: xxswapd 0, 34
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; CHECK-NEXT: mffprd 3, 0
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; CHECK-NEXT: clrldi 3, 3, 48
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; CHECK-NEXT: extsh 3, 3
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; CHECK-NEXT: blr
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entry:
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%0 = load <16 x i16>, ptr %addr, align 2
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%1 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> %0)
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ret i16 %1
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}
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define signext i32 @vecop_uses2(ptr %a, ptr %b, ptr %c) {
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; CHECK-LABEL: vecop_uses2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxvd2x 0, 0, 3
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; CHECK-NEXT: lxvd2x 1, 0, 4
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; CHECK-NEXT: xxswapd 34, 0
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; CHECK-NEXT: xxswapd 35, 1
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; CHECK-NEXT: xxsldwi 0, 34, 34, 3
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; CHECK-NEXT: vmuluwm 2, 3, 2
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; CHECK-NEXT: mffprwz 3, 0
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; CHECK-NEXT: xxswapd 0, 34
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; CHECK-NEXT: extsw 3, 3
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; CHECK-NEXT: stxvd2x 0, 0, 5
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; CHECK-NEXT: blr
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entry:
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%0 = load <4 x i32>, ptr %a, align 4
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%1 = load <4 x i32>, ptr %b, align 4
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%2 = mul <4 x i32> %1, %0
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store <4 x i32> %2, ptr %c, align 4
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%3 = extractelement <4 x i32> %0, i32 3
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ret i32 %3
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}
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declare <16 x i8> @llvm.ppc.altivec.vavgsb(<16 x i8>, <16 x i8>)
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declare i16 @llvm.vector.reduce.smin.v16i16(<16 x i16>)
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