a2b5b584a5
Compressed instructions usually require one of the source registers to also be the source register. The register allocator doesn't have that bias on its own. This patch adds register allocation hints to introduce this bias. I've started with ADDI, ADDIW, and SLLI. These all have a 5-bit field for the register. If the source and dest register are the same they are guaranteed to compress as long as the immediate is also 6 bits. This code was inspired by similar code from the SystemZ target. Reviewed By: reames Differential Revision: https://reviews.llvm.org/D138242
237 lines
5.8 KiB
LLVM
237 lines
5.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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; Test for handling of AND with constant. If this constant exceeds simm12 and
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; also is a non-empty sequence of ones starting at the least significant bit
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; with the remainder zero, we can replace it with SLLI + SLRI
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define i32 @and32_0x7ff(i32 %x) {
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; RV32I-LABEL: and32_0x7ff:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 2047
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and32_0x7ff:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, 2047
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; RV64I-NEXT: ret
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%a = and i32 %x, 2047
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ret i32 %a
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}
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define i32 @and32_0xfff(i32 %x) {
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; RV32I-LABEL: and32_0xfff:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 20
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; RV32I-NEXT: srli a0, a0, 20
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and32_0xfff:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 52
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; RV64I-NEXT: srli a0, a0, 52
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; RV64I-NEXT: ret
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%a = and i32 %x, 4095
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ret i32 %a
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}
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define i64 @and64_0x7ff(i64 %x) {
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; RV32I-LABEL: and64_0x7ff:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 2047
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; RV32I-NEXT: li a1, 0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and64_0x7ff:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, 2047
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; RV64I-NEXT: ret
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%a = and i64 %x, 2047
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ret i64 %a
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}
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define i64 @and64_0xfff(i64 %x) {
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; RV32I-LABEL: and64_0xfff:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 20
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; RV32I-NEXT: srli a0, a0, 20
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; RV32I-NEXT: li a1, 0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and64_0xfff:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 52
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; RV64I-NEXT: srli a0, a0, 52
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; RV64I-NEXT: ret
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%a = and i64 %x, 4095
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ret i64 %a
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}
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; Test for handling of AND with constant. If this constant exceeds simm32 and
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; also is a non-empty sequence of ones starting at the most significant bit
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; with the remainder zero, we can replace it with SRLI + SLLI.
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define i32 @and32_0x7ffff000(i32 %x) {
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; RV32I-LABEL: and32_0x7ffff000:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 524287
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and32_0x7ffff000:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, 524287
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: ret
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%a = and i32 %x, 2147479552
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ret i32 %a
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}
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define i32 @and32_0xfffff000(i32 %x) {
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; RV32I-LABEL: and32_0xfffff000:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 1048575
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and32_0xfffff000:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, 1048575
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: ret
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%a = and i32 %x, -4096
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ret i32 %a
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}
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define i32 @and32_0xfffffa00(i32 %x) {
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; RV32I-LABEL: and32_0xfffffa00:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, -1536
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and32_0xfffffa00:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, -1536
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; RV64I-NEXT: ret
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%a = and i32 %x, -1536
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ret i32 %a
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}
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define i64 @and64_0x7ffffffffffff000(i64 %x) {
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; RV32I-LABEL: and64_0x7ffffffffffff000:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a2, 1048575
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; RV32I-NEXT: and a0, a0, a2
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; RV32I-NEXT: slli a1, a1, 1
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; RV32I-NEXT: srli a1, a1, 1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and64_0x7ffffffffffff000:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, 1048574
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; RV64I-NEXT: srli a1, a1, 1
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: ret
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%a = and i64 %x, 9223372036854771712
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ret i64 %a
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}
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define i64 @and64_0xfffffffffffff000(i64 %x) {
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; RV32I-LABEL: and64_0xfffffffffffff000:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a2, 1048575
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; RV32I-NEXT: and a0, a0, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and64_0xfffffffffffff000:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, 1048575
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: ret
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%a = and i64 %x, -4096
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ret i64 %a
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}
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define i64 @and64_0xfffffffffffffa00(i64 %x) {
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; RV32I-LABEL: and64_0xfffffffffffffa00:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, -1536
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and64_0xfffffffffffffa00:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, -1536
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; RV64I-NEXT: ret
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%a = and i64 %x, -1536
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ret i64 %a
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}
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define i64 @and64_0xffffffff00000000(i64 %x) {
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; RV32I-LABEL: and64_0xffffffff00000000:
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; RV32I: # %bb.0:
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; RV32I-NEXT: li a0, 0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and64_0xffffffff00000000:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: ret
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%a = and i64 %x, -4294967296
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ret i64 %a
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}
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define i64 @and64_0x7fffffff00000000(i64 %x) {
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; RV32I-LABEL: and64_0x7fffffff00000000:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a1, a1, 1
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; RV32I-NEXT: srli a1, a1, 1
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; RV32I-NEXT: li a0, 0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and64_0x7fffffff00000000:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, 524288
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; RV64I-NEXT: addiw a1, a1, -1
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; RV64I-NEXT: slli a1, a1, 32
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: ret
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%a = and i64 %x, 9223372032559808512
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ret i64 %a
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}
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define i64 @and64_0xffffffff80000000(i64 %x) {
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; RV32I-LABEL: and64_0xffffffff80000000:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a2, 524288
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; RV32I-NEXT: and a0, a0, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and64_0xffffffff80000000:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, 524288
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: ret
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%a = and i64 %x, -2147483648
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ret i64 %a
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}
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define i64 @and64_0x00000000fffffff8(i64 %x) {
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; RV32I-LABEL: and64_0x00000000fffffff8:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, -8
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; RV32I-NEXT: li a1, 0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and64_0x00000000fffffff8:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srliw a0, a0, 3
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; RV64I-NEXT: slli a0, a0, 3
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; RV64I-NEXT: ret
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%a = and i64 %x, 4294967288
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ret i64 %a
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}
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