d64d3c5a8f
SLLI and ADD are more compressible than SLLIW and ADDW. SLLI/ADD both have a 5-bit register encoding. SLLIW/ADDW have a 3-bit register encoding. They both require the dest to also be one of the sources. We aggressively form ADDW/SLLIW as it helps hasAllWBitUsers in RISCVISelDAGToDAG to not require recursion. So we need a pass to remove excessive -w suffixes. Differential Revision: https://reviews.llvm.org/D139948
84 lines
2.1 KiB
LLVM
84 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
|
|
|
|
define i32 @f(i1 %0, i32 %1, ptr %2) {
|
|
; CHECK-LABEL: f:
|
|
; CHECK: # %bb.0: # %BB
|
|
; CHECK-NEXT: slli a3, a1, 11
|
|
; CHECK-NEXT: slli a1, a1, 12
|
|
; CHECK-NEXT: subw a1, a1, a3
|
|
; CHECK-NEXT: slli a0, a0, 63
|
|
; CHECK-NEXT: srai a0, a0, 63
|
|
; CHECK-NEXT: li a3, 1
|
|
; CHECK-NEXT: slli a3, a3, 11
|
|
; CHECK-NEXT: or a0, a0, a3
|
|
; CHECK-NEXT: sw a1, 0(a2)
|
|
; CHECK-NEXT: ret
|
|
BB:
|
|
%I = select i1 %0, i32 -1, i32 0
|
|
%I1 = mul i32 %1, 2048
|
|
%I2 = or i32 2048, %I
|
|
store i32 %I1, ptr %2
|
|
ret i32 %I2
|
|
}
|
|
|
|
define i32 @g(i1 %0, i32 %1, ptr %2) {
|
|
; CHECK-LABEL: g:
|
|
; CHECK: # %bb.0: # %BB
|
|
; CHECK-NEXT: slli a3, a1, 11
|
|
; CHECK-NEXT: slli a1, a1, 12
|
|
; CHECK-NEXT: subw a1, a1, a3
|
|
; CHECK-NEXT: andi a0, a0, 1
|
|
; CHECK-NEXT: addi a0, a0, -1
|
|
; CHECK-NEXT: li a3, 1
|
|
; CHECK-NEXT: slli a3, a3, 11
|
|
; CHECK-NEXT: or a0, a0, a3
|
|
; CHECK-NEXT: sw a1, 0(a2)
|
|
; CHECK-NEXT: ret
|
|
BB:
|
|
%I = select i1 %0, i32 0, i32 -1
|
|
%I1 = mul i32 %1, 2048
|
|
%I2 = or i32 2048, %I
|
|
store i32 %I1, ptr %2
|
|
ret i32 %I2
|
|
}
|
|
|
|
define i32 @h(i1 %0, i32 %1, ptr %2) {
|
|
; CHECK-LABEL: h:
|
|
; CHECK: # %bb.0: # %BB
|
|
; CHECK-NEXT: slli a3, a1, 11
|
|
; CHECK-NEXT: slli a1, a1, 12
|
|
; CHECK-NEXT: subw a1, a1, a3
|
|
; CHECK-NEXT: andi a0, a0, 1
|
|
; CHECK-NEXT: slli a0, a0, 11
|
|
; CHECK-NEXT: sw a1, 0(a2)
|
|
; CHECK-NEXT: ret
|
|
BB:
|
|
%I = select i1 %0, i32 -1, i32 0
|
|
%I1 = mul i32 %1, 2048
|
|
%I2 = and i32 2048, %I
|
|
store i32 %I1, ptr %2
|
|
ret i32 %I2
|
|
}
|
|
|
|
define i32 @i(i1 %0, i32 %1, ptr %2) {
|
|
; CHECK-LABEL: i:
|
|
; CHECK: # %bb.0: # %BB
|
|
; CHECK-NEXT: andi a0, a0, 1
|
|
; CHECK-NEXT: slli a3, a1, 11
|
|
; CHECK-NEXT: slli a1, a1, 12
|
|
; CHECK-NEXT: subw a1, a1, a3
|
|
; CHECK-NEXT: addi a0, a0, -1
|
|
; CHECK-NEXT: li a3, 1
|
|
; CHECK-NEXT: slli a3, a3, 11
|
|
; CHECK-NEXT: and a0, a0, a3
|
|
; CHECK-NEXT: sw a1, 0(a2)
|
|
; CHECK-NEXT: ret
|
|
BB:
|
|
%I = select i1 %0, i32 0, i32 -1
|
|
%I1 = mul i32 %1, 2048
|
|
%I2 = and i32 2048, %I
|
|
store i32 %I1, ptr %2
|
|
ret i32 %I2
|
|
}
|