70a64fe7b1
This extension does not appear to be on its way to ratification. Out of the unratified bitmanip extensions, this one had the largest impact on the compiler. Posting this patch to start a discussion about whether we should remove these extensions. We'll talk more at the RISC-V sync meeting this Thursday. Reviewed By: asb, reames Differential Revision: https://reviews.llvm.org/D133834
85 lines
2.4 KiB
LLVM
85 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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;; There are a few different ways to lower (select (and A, B), X, Y). This test
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;; ensures that we do so with as few branches as possible.
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define signext i32 @select_of_and(i1 zeroext %a, i1 zeroext %b, i32 signext %c, i32 signext %d) nounwind {
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; RV32I-LABEL: select_of_and:
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; RV32I: # %bb.0:
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; RV32I-NEXT: and a1, a0, a1
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: bnez a1, .LBB0_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: mv a0, a3
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; RV32I-NEXT: .LBB0_2:
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: select_of_and:
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; RV64I: # %bb.0:
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; RV64I-NEXT: and a1, a0, a1
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; RV64I-NEXT: mv a0, a2
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; RV64I-NEXT: bnez a1, .LBB0_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: mv a0, a3
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; RV64I-NEXT: .LBB0_2:
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; RV64I-NEXT: ret
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%1 = and i1 %a, %b
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%2 = select i1 %1, i32 %c, i32 %d
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ret i32 %2
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}
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declare signext i32 @both() nounwind
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declare signext i32 @neither() nounwind
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define signext i32 @if_of_and(i1 zeroext %a, i1 zeroext %b) nounwind {
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; RV32I-LABEL: if_of_and:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: beqz a0, .LBB1_2
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; RV32I-NEXT: # %bb.1: # %if.then
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; RV32I-NEXT: call both@plt
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; RV32I-NEXT: j .LBB1_3
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; RV32I-NEXT: .LBB1_2: # %if.else
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; RV32I-NEXT: call neither@plt
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; RV32I-NEXT: .LBB1_3: # %if.end
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: if_of_and:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: beqz a0, .LBB1_2
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; RV64I-NEXT: # %bb.1: # %if.then
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; RV64I-NEXT: call both@plt
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; RV64I-NEXT: j .LBB1_3
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; RV64I-NEXT: .LBB1_2: # %if.else
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; RV64I-NEXT: call neither@plt
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; RV64I-NEXT: .LBB1_3: # %if.end
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = and i1 %a, %b
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br i1 %1, label %if.then, label %if.else
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if.then:
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%2 = tail call i32 @both()
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br label %if.end
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if.else:
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%3 = tail call i32 @neither()
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br label %if.end
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if.end:
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%4 = phi i32 [%2, %if.then], [%3, %if.else]
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ret i32 %4
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}
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