a1710eb3cd
The LIT test cases were migrated with the script provided by Nikita Popov. No manual changes were made. Committed without review since no functional changes, after consultation with uweigand.
183 lines
5.3 KiB
LLVM
183 lines
5.3 KiB
LLVM
; Test 64-bit compare and swap.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Check CDSG without a displacement.
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define i128 @f1(i128 %cmp, i128 %swap, ptr %src) {
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; CHECK-LABEL: f1:
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; CHECK-DAG: lg %r1, 8(%r4)
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; CHECK-DAG: lg %r0, 0(%r4)
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; CHECK-DAG: lg %r13, 8(%r3)
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; CHECK-DAG: lg %r12, 0(%r3)
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; CHECK: cdsg %r12, %r0, 0(%r5)
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; CHECK-DAG: stg %r13, 8(%r2)
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; CHECK-DAG: stg %r12, 0(%r2)
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; CHECK: br %r14
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%pairval = cmpxchg ptr %src, i128 %cmp, i128 %swap seq_cst seq_cst
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%val = extractvalue { i128, i1 } %pairval, 0
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ret i128 %val
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}
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; Check the high end of the aligned CDSG range.
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define i128 @f2(i128 %cmp, i128 %swap, ptr %src) {
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; CHECK-LABEL: f2:
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; CHECK: cdsg {{%r[0-9]+}}, {{%r[0-9]+}}, 524272(%r5)
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; CHECK: br %r14
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%ptr = getelementptr i128, ptr %src, i128 32767
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%pairval = cmpxchg ptr %ptr, i128 %cmp, i128 %swap seq_cst seq_cst
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%val = extractvalue { i128, i1 } %pairval, 0
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ret i128 %val
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}
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; Check the next doubleword up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i128 @f3(i128 %cmp, i128 %swap, ptr %src) {
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; CHECK-LABEL: f3:
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; CHECK: agfi %r5, 524288
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; CHECK: cdsg {{%r[0-9]+}}, {{%r[0-9]+}}, 0(%r5)
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; CHECK: br %r14
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%ptr = getelementptr i128, ptr %src, i128 32768
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%pairval = cmpxchg ptr %ptr, i128 %cmp, i128 %swap seq_cst seq_cst
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%val = extractvalue { i128, i1 } %pairval, 0
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ret i128 %val
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}
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; Check the high end of the negative aligned CDSG range.
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define i128 @f4(i128 %cmp, i128 %swap, ptr %src) {
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; CHECK-LABEL: f4:
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; CHECK: cdsg {{%r[0-9]+}}, {{%r[0-9]+}}, -16(%r5)
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; CHECK: br %r14
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%ptr = getelementptr i128, ptr %src, i128 -1
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%pairval = cmpxchg ptr %ptr, i128 %cmp, i128 %swap seq_cst seq_cst
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%val = extractvalue { i128, i1 } %pairval, 0
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ret i128 %val
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}
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; Check the low end of the CDSG range.
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define i128 @f5(i128 %cmp, i128 %swap, ptr %src) {
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; CHECK-LABEL: f5:
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; CHECK: cdsg {{%r[0-9]+}}, {{%r[0-9]+}}, -524288(%r5)
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; CHECK: br %r14
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%ptr = getelementptr i128, ptr %src, i128 -32768
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%pairval = cmpxchg ptr %ptr, i128 %cmp, i128 %swap seq_cst seq_cst
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%val = extractvalue { i128, i1 } %pairval, 0
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ret i128 %val
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}
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; Check the next doubleword down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i128 @f6(i128 %cmp, i128 %swap, ptr %src) {
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; CHECK-LABEL: f6:
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; CHECK: agfi %r5, -524304
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; CHECK: cdsg {{%r[0-9]+}}, {{%r[0-9]+}}, 0(%r5)
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; CHECK: br %r14
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%ptr = getelementptr i128, ptr %src, i128 -32769
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%pairval = cmpxchg ptr %ptr, i128 %cmp, i128 %swap seq_cst seq_cst
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%val = extractvalue { i128, i1 } %pairval, 0
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ret i128 %val
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}
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; Check that CDSG does not allow an index.
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define i128 @f7(i128 %cmp, i128 %swap, i64 %src, i64 %index) {
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; CHECK-LABEL: f7:
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; CHECK: agr %r5, %r6
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; CHECK: cdsg {{%r[0-9]+}}, {{%r[0-9]+}}, 0(%r5)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%ptr = inttoptr i64 %add1 to ptr
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%pairval = cmpxchg ptr %ptr, i128 %cmp, i128 %swap seq_cst seq_cst
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%val = extractvalue { i128, i1 } %pairval, 0
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ret i128 %val
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}
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; Check that a constant %cmp value is loaded into a register first.
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define i128 @f8(i128 %swap, ptr %ptr) {
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; CHECK-LABEL: f8:
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; CHECK: lghi {{%r[0-9]+}}, 1001
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; CHECK: cdsg {{%r[0-9]+}}, {{%r[0-9]+}}, 0(%r4)
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; CHECK: br %r14
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%pairval = cmpxchg ptr %ptr, i128 1001, i128 %swap seq_cst seq_cst
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%val = extractvalue { i128, i1 } %pairval, 0
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ret i128 %val
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}
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; Check that a constant %swap value is loaded into a register first.
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define i128 @f9(i128 %cmp, ptr %ptr) {
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; CHECK-LABEL: f9:
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; CHECK: lghi {{%r[0-9]+}}, 1002
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; CHECK: cdsg {{%r[0-9]+}}, {{%r[0-9]+}}, 0(%r4)
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; CHECK: br %r14
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%pairval = cmpxchg ptr %ptr, i128 %cmp, i128 1002 seq_cst seq_cst
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%val = extractvalue { i128, i1 } %pairval, 0
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ret i128 %val
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}
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; Check generating the comparison result.
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; CHECK-LABEL: f10
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; CHECK-DAG: lg %r1, 8(%r3)
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; CHECK-DAG: lg %r0, 0(%r3)
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; CHECK-DAG: lg %r13, 8(%r2)
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; CHECK-DAG: lg %r12, 0(%r2)
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; CHECK: cdsg %r12, %r0, 0(%r4)
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; CHECK-NEXT: ipm %r2
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; CHECK-NEXT: afi %r2, -268435456
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; CHECK-NEXT: srl %r2, 31
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; CHECK: br %r14
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define i32 @f10(i128 %cmp, i128 %swap, ptr %src) {
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%pairval = cmpxchg ptr %src, i128 %cmp, i128 %swap seq_cst seq_cst
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%val = extractvalue { i128, i1 } %pairval, 1
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%res = zext i1 %val to i32
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ret i32 %res
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}
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declare void @g()
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; Check using the comparison result for a branch.
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; CHECK-LABEL: f11
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; CHECK-DAG: lg %r1, 8(%r3)
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; CHECK-DAG: lg %r0, 0(%r3)
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; CHECK-DAG: lg %r13, 8(%r2)
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; CHECK-DAG: lg %r12, 0(%r2)
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; CHECK: cdsg %r12, %r0, 0(%r4)
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; CHECK-NEXT: jl [[LABEL:\.[^ ]*]]
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; CHECK: jg g
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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define void @f11(i128 %cmp, i128 %swap, ptr %src) {
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%pairval = cmpxchg ptr %src, i128 %cmp, i128 %swap seq_cst seq_cst
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%cond = extractvalue { i128, i1 } %pairval, 1
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br i1 %cond, label %call, label %exit
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call:
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tail call void @g()
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br label %exit
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exit:
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ret void
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}
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; ... and the same with the inverted direction.
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; CHECK-LABEL: f12
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; CHECK-DAG: lg %r1, 8(%r3)
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; CHECK-DAG: lg %r0, 0(%r3)
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; CHECK-DAG: lg %r13, 8(%r2)
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; CHECK-DAG: lg %r12, 0(%r2)
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; CHECK: cdsg %r12, %r0, 0(%r4)
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; CHECK-NEXT: jl [[LABEL:\.[^ ]*]]
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; CHECK: br %r14
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; CHECK: [[LABEL]]:
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; CHECK: jg g
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define void @f12(i128 %cmp, i128 %swap, ptr %src) {
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%pairval = cmpxchg ptr %src, i128 %cmp, i128 %swap seq_cst seq_cst
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%cond = extractvalue { i128, i1 } %pairval, 1
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br i1 %cond, label %exit, label %call
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call:
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tail call void @g()
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br label %exit
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exit:
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ret void
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}
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