a1710eb3cd
The LIT test cases were migrated with the script provided by Nikita Popov. No manual changes were made. Committed without review since no functional changes, after consultation with uweigand.
146 lines
4.0 KiB
LLVM
146 lines
4.0 KiB
LLVM
; Test 128-bit addition in which the second operand is variable.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
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declare ptr@foo()
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; Test register addition.
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define void @f1(ptr %ptr) {
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; CHECK-LABEL: f1:
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; CHECK: algr
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; CHECK: alcgr
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; CHECK: br %r14
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%value = load i128, ptr %ptr
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%add = add i128 %value, %value
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store i128 %add, ptr %ptr
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ret void
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}
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; Test memory addition with no offset. Making the load of %a volatile
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; should force the memory operand to be %b.
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define void @f2(ptr %aptr, i64 %addr) {
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; CHECK-LABEL: f2:
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; CHECK: alg {{%r[0-5]}}, 8(%r3)
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; CHECK: alcg {{%r[0-5]}}, 0(%r3)
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; CHECK: br %r14
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%bptr = inttoptr i64 %addr to ptr
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%a = load volatile i128, ptr %aptr
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%b = load i128, ptr %bptr
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%add = add i128 %a, %b
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store i128 %add, ptr %aptr
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ret void
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}
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; Test the highest aligned offset that is in range of both ALG and ALCG.
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define void @f3(ptr %aptr, i64 %base) {
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; CHECK-LABEL: f3:
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; CHECK: alg {{%r[0-5]}}, 524280(%r3)
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; CHECK: alcg {{%r[0-5]}}, 524272(%r3)
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; CHECK: br %r14
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%addr = add i64 %base, 524272
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%bptr = inttoptr i64 %addr to ptr
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%a = load volatile i128, ptr %aptr
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%b = load i128, ptr %bptr
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%add = add i128 %a, %b
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store i128 %add, ptr %aptr
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ret void
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}
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; Test the next doubleword up, which requires separate address logic for ALG.
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define void @f4(ptr %aptr, i64 %base) {
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; CHECK-LABEL: f4:
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; CHECK: lay [[BASE:%r[1-5]]], 524280(%r3)
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; CHECK: alg {{%r[0-5]}}, 8([[BASE]])
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; CHECK: alcg {{%r[0-5]}}, 524280(%r3)
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; CHECK: br %r14
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%addr = add i64 %base, 524280
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%bptr = inttoptr i64 %addr to ptr
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%a = load volatile i128, ptr %aptr
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%b = load i128, ptr %bptr
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%add = add i128 %a, %b
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store i128 %add, ptr %aptr
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ret void
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}
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; Test the next doubleword after that, which requires separate logic for
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; both instructions.
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define void @f5(ptr %aptr, i64 %base) {
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; CHECK-LABEL: f5:
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; CHECK: alg {{%r[0-5]}}, 8({{%r[1-5]}})
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; CHECK: alcg {{%r[0-5]}}, 0({{%r[1-5]}})
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; CHECK: br %r14
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%addr = add i64 %base, 524288
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%bptr = inttoptr i64 %addr to ptr
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%a = load volatile i128, ptr %aptr
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%b = load i128, ptr %bptr
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%add = add i128 %a, %b
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store i128 %add, ptr %aptr
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ret void
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}
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; Test the lowest displacement that is in range of both ALG and ALCG.
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define void @f6(ptr %aptr, i64 %base) {
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; CHECK-LABEL: f6:
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; CHECK: alg {{%r[0-5]}}, -524280(%r3)
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; CHECK: alcg {{%r[0-5]}}, -524288(%r3)
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; CHECK: br %r14
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%addr = add i64 %base, -524288
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%bptr = inttoptr i64 %addr to ptr
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%a = load volatile i128, ptr %aptr
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%b = load i128, ptr %bptr
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%add = add i128 %a, %b
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store i128 %add, ptr %aptr
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ret void
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}
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; Test the next doubleword down, which is out of range of the ALCG.
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define void @f7(ptr %aptr, i64 %base) {
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; CHECK-LABEL: f7:
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; CHECK: alg {{%r[0-5]}}, -524288(%r3)
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; CHECK: alcg {{%r[0-5]}}, 0({{%r[1-5]}})
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; CHECK: br %r14
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%addr = add i64 %base, -524296
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%bptr = inttoptr i64 %addr to ptr
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%a = load volatile i128, ptr %aptr
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%b = load i128, ptr %bptr
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%add = add i128 %a, %b
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store i128 %add, ptr %aptr
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ret void
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}
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; Check that additions of spilled values can use ALG and ALCG rather than
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; ALGR and ALCGR.
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define void @f8(ptr %ptr0) {
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; CHECK-LABEL: f8:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: alg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
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; CHECK: alcg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
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; CHECK: br %r14
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%ptr1 = getelementptr i128, ptr %ptr0, i128 2
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%ptr2 = getelementptr i128, ptr %ptr0, i128 4
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%ptr3 = getelementptr i128, ptr %ptr0, i128 6
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%ptr4 = getelementptr i128, ptr %ptr0, i128 8
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%ptr5 = getelementptr i128, ptr %ptr0, i128 10
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%val0 = load i128, ptr %ptr0
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%val1 = load i128, ptr %ptr1
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%val2 = load i128, ptr %ptr2
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%val3 = load i128, ptr %ptr3
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%val4 = load i128, ptr %ptr4
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%val5 = load i128, ptr %ptr5
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%retptr = call ptr@foo()
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%ret = load i128, ptr %retptr
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%add0 = add i128 %ret, %val0
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%add1 = add i128 %add0, %val1
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%add2 = add i128 %add1, %val2
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%add3 = add i128 %add2, %val3
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%add4 = add i128 %add3, %val4
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%add5 = add i128 %add4, %val5
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store i128 %add5, ptr %retptr
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ret void
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}
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