a1710eb3cd
The LIT test cases were migrated with the script provided by Nikita Popov. No manual changes were made. Committed without review since no functional changes, after consultation with uweigand.
210 lines
5.8 KiB
LLVM
210 lines
5.8 KiB
LLVM
; Test zero extensions from a halfword to an i32. The tests here
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; assume z10 register pressure, without the high words being available.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
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; Test register extension, starting with an i32.
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define i32 @f1(i32 %a) {
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; CHECK-LABEL: f1:
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; CHECK: llhr %r2, %r2
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; CHECK: br %r14
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%half = trunc i32 %a to i16
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%ext = zext i16 %half to i32
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ret i32 %ext
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}
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; ...and again with an i64.
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define i32 @f2(i64 %a) {
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; CHECK-LABEL: f2:
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; CHECK: llhr %r2, %r2
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; CHECK: br %r14
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%half = trunc i64 %a to i16
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%ext = zext i16 %half to i32
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ret i32 %ext
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}
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; Check ANDs that are equivalent to zero extension.
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define i32 @f3(i32 %a) {
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; CHECK-LABEL: f3:
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; CHECK: llhr %r2, %r2
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; CHECK: br %r14
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%ext = and i32 %a, 65535
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ret i32 %ext
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}
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; Check LLH with no displacement.
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define i32 @f4(ptr %src) {
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; CHECK-LABEL: f4:
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; CHECK: llh %r2, 0(%r2)
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; CHECK: br %r14
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%half = load i16, ptr %src
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%ext = zext i16 %half to i32
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ret i32 %ext
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}
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; Check the high end of the LLH range.
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define i32 @f5(ptr %src) {
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; CHECK-LABEL: f5:
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; CHECK: llh %r2, 524286(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i16, ptr %src, i64 262143
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%half = load i16, ptr %ptr
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%ext = zext i16 %half to i32
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ret i32 %ext
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}
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; Check the next halfword up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i32 @f6(ptr %src) {
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; CHECK-LABEL: f6:
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; CHECK: agfi %r2, 524288
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; CHECK: llh %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i16, ptr %src, i64 262144
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%half = load i16, ptr %ptr
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%ext = zext i16 %half to i32
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ret i32 %ext
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}
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; Check the high end of the negative LLH range.
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define i32 @f7(ptr %src) {
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; CHECK-LABEL: f7:
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; CHECK: llh %r2, -2(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i16, ptr %src, i64 -1
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%half = load i16, ptr %ptr
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%ext = zext i16 %half to i32
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ret i32 %ext
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}
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; Check the low end of the LLH range.
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define i32 @f8(ptr %src) {
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; CHECK-LABEL: f8:
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; CHECK: llh %r2, -524288(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i16, ptr %src, i64 -262144
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%half = load i16, ptr %ptr
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%ext = zext i16 %half to i32
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ret i32 %ext
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}
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; Check the next halfword down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i32 @f9(ptr %src) {
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; CHECK-LABEL: f9:
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; CHECK: agfi %r2, -524290
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; CHECK: llh %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i16, ptr %src, i64 -262145
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%half = load i16, ptr %ptr
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%ext = zext i16 %half to i32
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ret i32 %ext
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}
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; Check that LLH allows an index
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define i32 @f10(i64 %src, i64 %index) {
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; CHECK-LABEL: f10:
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; CHECK: llh %r2, 524287(%r3,%r2)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to ptr
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%half = load i16, ptr %ptr
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%ext = zext i16 %half to i32
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ret i32 %ext
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}
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; Test a case where we spill the source of at least one LLHR. We want
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; to use LLH if possible.
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define void @f11(ptr %ptr) {
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; CHECK-LABEL: f11:
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; CHECK: llh {{%r[0-9]+}}, 186(%r15)
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; CHECK: br %r14
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%val0 = load volatile i32, ptr %ptr
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%val1 = load volatile i32, ptr %ptr
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%val2 = load volatile i32, ptr %ptr
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%val3 = load volatile i32, ptr %ptr
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%val4 = load volatile i32, ptr %ptr
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%val5 = load volatile i32, ptr %ptr
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%val6 = load volatile i32, ptr %ptr
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%val7 = load volatile i32, ptr %ptr
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%val8 = load volatile i32, ptr %ptr
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%val9 = load volatile i32, ptr %ptr
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%val10 = load volatile i32, ptr %ptr
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%val11 = load volatile i32, ptr %ptr
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%val12 = load volatile i32, ptr %ptr
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%val13 = load volatile i32, ptr %ptr
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%val14 = load volatile i32, ptr %ptr
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%val15 = load volatile i32, ptr %ptr
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%trunc0 = trunc i32 %val0 to i16
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%trunc1 = trunc i32 %val1 to i16
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%trunc2 = trunc i32 %val2 to i16
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%trunc3 = trunc i32 %val3 to i16
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%trunc4 = trunc i32 %val4 to i16
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%trunc5 = trunc i32 %val5 to i16
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%trunc6 = trunc i32 %val6 to i16
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%trunc7 = trunc i32 %val7 to i16
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%trunc8 = trunc i32 %val8 to i16
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%trunc9 = trunc i32 %val9 to i16
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%trunc10 = trunc i32 %val10 to i16
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%trunc11 = trunc i32 %val11 to i16
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%trunc12 = trunc i32 %val12 to i16
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%trunc13 = trunc i32 %val13 to i16
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%trunc14 = trunc i32 %val14 to i16
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%trunc15 = trunc i32 %val15 to i16
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%ext0 = zext i16 %trunc0 to i32
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%ext1 = zext i16 %trunc1 to i32
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%ext2 = zext i16 %trunc2 to i32
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%ext3 = zext i16 %trunc3 to i32
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%ext4 = zext i16 %trunc4 to i32
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%ext5 = zext i16 %trunc5 to i32
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%ext6 = zext i16 %trunc6 to i32
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%ext7 = zext i16 %trunc7 to i32
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%ext8 = zext i16 %trunc8 to i32
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%ext9 = zext i16 %trunc9 to i32
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%ext10 = zext i16 %trunc10 to i32
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%ext11 = zext i16 %trunc11 to i32
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%ext12 = zext i16 %trunc12 to i32
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%ext13 = zext i16 %trunc13 to i32
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%ext14 = zext i16 %trunc14 to i32
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%ext15 = zext i16 %trunc15 to i32
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store volatile i32 %val0, ptr %ptr
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store volatile i32 %val1, ptr %ptr
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store volatile i32 %val2, ptr %ptr
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store volatile i32 %val3, ptr %ptr
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store volatile i32 %val4, ptr %ptr
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store volatile i32 %val5, ptr %ptr
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store volatile i32 %val6, ptr %ptr
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store volatile i32 %val7, ptr %ptr
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store volatile i32 %val8, ptr %ptr
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store volatile i32 %val9, ptr %ptr
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store volatile i32 %val10, ptr %ptr
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store volatile i32 %val11, ptr %ptr
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store volatile i32 %val12, ptr %ptr
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store volatile i32 %val13, ptr %ptr
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store volatile i32 %val14, ptr %ptr
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store volatile i32 %val15, ptr %ptr
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store volatile i32 %ext0, ptr %ptr
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store volatile i32 %ext1, ptr %ptr
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store volatile i32 %ext2, ptr %ptr
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store volatile i32 %ext3, ptr %ptr
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store volatile i32 %ext4, ptr %ptr
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store volatile i32 %ext5, ptr %ptr
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store volatile i32 %ext6, ptr %ptr
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store volatile i32 %ext7, ptr %ptr
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store volatile i32 %ext8, ptr %ptr
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store volatile i32 %ext9, ptr %ptr
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store volatile i32 %ext10, ptr %ptr
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store volatile i32 %ext11, ptr %ptr
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store volatile i32 %ext12, ptr %ptr
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store volatile i32 %ext13, ptr %ptr
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store volatile i32 %ext14, ptr %ptr
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store volatile i32 %ext15, ptr %ptr
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ret void
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}
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