189900eb14
This stops reporting CostPerUse 1 for `R8`-`R15` and `XMM8`-`XMM31`.
This was previously done because instruction encoding require a REX
prefix when using them resulting in longer instruction encodings. I
found that this regresses the quality of the register allocation as the
costs impose an ordering on eviction candidates. I also feel that there
is a bit of an impedance mismatch as the actual costs occure when
encoding instructions using those registers, but the order of VReg
assignments is not primarily ordered by number of Defs+Uses.
I did extensive measurements with the llvm-test-suite wiht SPEC2006 +
SPEC2017 included, internal services showed similar patterns. Generally
there are a log of improvements but also a lot of regression. But on
average the allocation quality seems to improve at a small code size
regression.
Results for measuring static and dynamic instruction counts:
Dynamic Counts (scaled by execution frequency) / Optimization Remarks:
Spills+FoldedSpills -5.6%
Reloads+FoldedReloads -4.2%
Copies -0.1%
Static / LLVM Statistics:
regalloc.NumSpills mean -1.6%, geomean -2.8%
regalloc.NumReloads mean -1.7%, geomean -3.1%
size..text mean +0.4%, geomean +0.4%
Static / LLVM Statistics:
mean -2.2%, geomean -3.1%) regalloc.NumSpills
mean -2.6%, geomean -3.9%) regalloc.NumReloads
mean +0.6%, geomean +0.6%) size..text
Static / LLVM Statistics:
regalloc.NumSpills mean -3.0%
regalloc.NumReloads mean -3.3%
size..text mean +0.3%, geomean +0.3%
Differential Revision: https://reviews.llvm.org/D133902
182 lines
7.1 KiB
LLVM
182 lines
7.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-macosx -mattr=+sse2 -verify-machineinstrs | FileCheck %s
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; After tail duplication, two copies in an early exit BB can be cancelled out.
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; rdar://10640363
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define i32 @t1(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: t1:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: testl %esi, %esi
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; CHECK-NEXT: je LBB0_4
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; CHECK-NEXT: ## %bb.1: ## %while.body.preheader
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; CHECK-NEXT: movl %esi, %edx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB0_2: ## %while.body
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: movl %edx, %ecx
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; CHECK-NEXT: cltd
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; CHECK-NEXT: idivl %ecx
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; CHECK-NEXT: testl %edx, %edx
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: jne LBB0_2
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; CHECK-NEXT: ## %bb.3: ## %while.end
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: LBB0_4:
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; CHECK-NEXT: retq
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entry:
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%cmp1 = icmp eq i32 %b, 0
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br i1 %cmp1, label %while.end, label %while.body
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while.body: ; preds = %entry, %while.body
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%a.addr.03 = phi i32 [ %b.addr.02, %while.body ], [ %a, %entry ]
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%b.addr.02 = phi i32 [ %rem, %while.body ], [ %b, %entry ]
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%rem = srem i32 %a.addr.03, %b.addr.02
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%cmp = icmp eq i32 %rem, 0
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br i1 %cmp, label %while.end, label %while.body
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while.end: ; preds = %while.body, %entry
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%a.addr.0.lcssa = phi i32 [ %a, %entry ], [ %b.addr.02, %while.body ]
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ret i32 %a.addr.0.lcssa
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}
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; Two movdqa (from phi-elimination) in the entry BB cancels out.
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; rdar://10428165
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define <8 x i16> @t2(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
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; CHECK-LABEL: t2:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
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; CHECK-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,1,2,4,5,6,7]
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; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; CHECK-NEXT: retq
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entry:
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%tmp8 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 undef, i32 undef, i32 7, i32 2, i32 8, i32 undef, i32 undef , i32 undef >
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ret <8 x i16> %tmp8
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}
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define i32 @t3(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: t3:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: testq %rsi, %rsi
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; CHECK-NEXT: je LBB2_4
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; CHECK-NEXT: ## %bb.1: ## %while.body.preheader
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; CHECK-NEXT: movq %rsi, %rdx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB2_2: ## %while.body
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: movq %rdx, %rcx
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; CHECK-NEXT: cqto
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; CHECK-NEXT: idivq %rcx
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; CHECK-NEXT: testq %rdx, %rdx
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; CHECK-NEXT: movq %rcx, %rax
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; CHECK-NEXT: jne LBB2_2
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; CHECK-NEXT: ## %bb.3: ## %while.end
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: LBB2_4:
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; CHECK-NEXT: retq
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entry:
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%cmp1 = icmp eq i64 %b, 0
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br i1 %cmp1, label %while.end, label %while.body
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while.body: ; preds = %entry, %while.body
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%a.addr.03 = phi i64 [ %b.addr.02, %while.body ], [ %a, %entry ]
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%b.addr.02 = phi i64 [ %rem, %while.body ], [ %b, %entry ]
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%rem = srem i64 %a.addr.03, %b.addr.02
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%cmp = icmp eq i64 %rem, 0
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br i1 %cmp, label %while.end, label %while.body
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while.end: ; preds = %while.body, %entry
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%a.addr.0.lcssa = phi i64 [ %a, %entry ], [ %b.addr.02, %while.body ]
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%t = trunc i64 %a.addr.0.lcssa to i32
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ret i32 %t
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}
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; Check that copy propagation does not kill thing like:
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; dst = copy src <-- do not kill that.
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; ... = op1 undef dst
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; ... = op2 dst <-- this is used here.
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define <16 x float> @foo(<16 x float> %x) {
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; CHECK-LABEL: foo:
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; CHECK: ## %bb.0: ## %bb
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; CHECK-NEXT: movaps %xmm3, %xmm9
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; CHECK-NEXT: movaps %xmm2, %xmm5
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; CHECK-NEXT: movaps %xmm0, %xmm7
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: movaps %xmm3, %xmm2
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; CHECK-NEXT: cmpltps %xmm0, %xmm2
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; CHECK-NEXT: movaps %xmm2, %xmm4
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; CHECK-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
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; CHECK-NEXT: movaps %xmm4, %xmm8
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; CHECK-NEXT: andnps %xmm2, %xmm8
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; CHECK-NEXT: movaps %xmm5, %xmm6
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; CHECK-NEXT: cmpltps %xmm0, %xmm6
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; CHECK-NEXT: movaps {{.*#+}} xmm11 = [9,10,11,12]
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; CHECK-NEXT: movaps %xmm6, %xmm2
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; CHECK-NEXT: orps %xmm11, %xmm2
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; CHECK-NEXT: movaps %xmm2, %xmm10
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; CHECK-NEXT: andnps %xmm6, %xmm10
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; CHECK-NEXT: cvttps2dq %xmm1, %xmm12
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; CHECK-NEXT: cmpltps %xmm0, %xmm1
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; CHECK-NEXT: movaps {{.*#+}} xmm13 = [5,6,7,8]
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; CHECK-NEXT: movaps %xmm1, %xmm6
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; CHECK-NEXT: orps %xmm13, %xmm6
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; CHECK-NEXT: movaps %xmm6, %xmm14
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; CHECK-NEXT: andnps %xmm1, %xmm14
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; CHECK-NEXT: cvttps2dq %xmm7, %xmm3
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; CHECK-NEXT: cmpltps %xmm0, %xmm7
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; CHECK-NEXT: movaps {{.*#+}} xmm15 = [1,2,3,4]
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; CHECK-NEXT: movaps %xmm7, %xmm0
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; CHECK-NEXT: orps %xmm15, %xmm0
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; CHECK-NEXT: movaps %xmm0, %xmm1
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; CHECK-NEXT: andnps %xmm7, %xmm1
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; CHECK-NEXT: andps %xmm15, %xmm0
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; CHECK-NEXT: cvtdq2ps %xmm3, %xmm3
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; CHECK-NEXT: andps %xmm3, %xmm0
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; CHECK-NEXT: movaps {{.*#+}} xmm3 = [1,1,1,1]
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; CHECK-NEXT: andps %xmm3, %xmm1
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; CHECK-NEXT: orps %xmm1, %xmm0
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; CHECK-NEXT: andps %xmm13, %xmm6
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; CHECK-NEXT: cvtdq2ps %xmm12, %xmm1
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; CHECK-NEXT: andps %xmm1, %xmm6
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; CHECK-NEXT: andps %xmm3, %xmm14
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; CHECK-NEXT: orps %xmm14, %xmm6
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; CHECK-NEXT: andps %xmm11, %xmm2
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; CHECK-NEXT: cvttps2dq %xmm5, %xmm1
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; CHECK-NEXT: cvtdq2ps %xmm1, %xmm1
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; CHECK-NEXT: andps %xmm1, %xmm2
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; CHECK-NEXT: andps %xmm3, %xmm10
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; CHECK-NEXT: orps %xmm10, %xmm2
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; CHECK-NEXT: andps %xmm3, %xmm8
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; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
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; CHECK-NEXT: cvttps2dq %xmm9, %xmm1
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; CHECK-NEXT: cvtdq2ps %xmm1, %xmm1
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; CHECK-NEXT: andps %xmm1, %xmm4
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; CHECK-NEXT: orps %xmm8, %xmm4
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; CHECK-NEXT: movaps %xmm6, %xmm1
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; CHECK-NEXT: movaps %xmm4, %xmm3
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; CHECK-NEXT: retq
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bb:
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%v3 = icmp slt <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>, zeroinitializer
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%v14 = zext <16 x i1> %v3 to <16 x i32>
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%v16 = fcmp olt <16 x float> %x, zeroinitializer
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%v17 = sext <16 x i1> %v16 to <16 x i32>
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%v18 = zext <16 x i1> %v16 to <16 x i32>
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%v19 = xor <16 x i32> %v14, %v18
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%v20 = or <16 x i32> %v17, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16>
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%v21 = fptosi <16 x float> %x to <16 x i32>
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%v22 = sitofp <16 x i32> %v21 to <16 x float>
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%v69 = fcmp ogt <16 x float> %v22, zeroinitializer
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%v75 = and <16 x i1> %v69, %v3
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%v77 = bitcast <16 x float> %v22 to <16 x i32>
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%v79 = sext <16 x i1> %v75 to <16 x i32>
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%v80 = and <16 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16>, %v79
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%v81 = xor <16 x i32> %v77, %v80
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%v82 = and <16 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16>, %v81
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%v83 = xor <16 x i32> %v19, %v82
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%v84 = and <16 x i32> %v83, %v20
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%v85 = xor <16 x i32> %v19, %v84
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%v86 = bitcast <16 x i32> %v85 to <16 x float>
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ret <16 x float> %v86
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}
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