189900eb14
This stops reporting CostPerUse 1 for `R8`-`R15` and `XMM8`-`XMM31`.
This was previously done because instruction encoding require a REX
prefix when using them resulting in longer instruction encodings. I
found that this regresses the quality of the register allocation as the
costs impose an ordering on eviction candidates. I also feel that there
is a bit of an impedance mismatch as the actual costs occure when
encoding instructions using those registers, but the order of VReg
assignments is not primarily ordered by number of Defs+Uses.
I did extensive measurements with the llvm-test-suite wiht SPEC2006 +
SPEC2017 included, internal services showed similar patterns. Generally
there are a log of improvements but also a lot of regression. But on
average the allocation quality seems to improve at a small code size
regression.
Results for measuring static and dynamic instruction counts:
Dynamic Counts (scaled by execution frequency) / Optimization Remarks:
Spills+FoldedSpills -5.6%
Reloads+FoldedReloads -4.2%
Copies -0.1%
Static / LLVM Statistics:
regalloc.NumSpills mean -1.6%, geomean -2.8%
regalloc.NumReloads mean -1.7%, geomean -3.1%
size..text mean +0.4%, geomean +0.4%
Static / LLVM Statistics:
mean -2.2%, geomean -3.1%) regalloc.NumSpills
mean -2.6%, geomean -3.9%) regalloc.NumReloads
mean +0.6%, geomean +0.6%) size..text
Static / LLVM Statistics:
regalloc.NumSpills mean -3.0%
regalloc.NumReloads mean -3.3%
size..text mean +0.3%, geomean +0.3%
Differential Revision: https://reviews.llvm.org/D133902
148 lines
4.7 KiB
LLVM
148 lines
4.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O3 --x86-asm-syntax=intel -mtriple=x86_64 -mattr=avx < %s | FileCheck %s
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define void @extracter0([4 x <4 x i1>] %matrix) {
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; CHECK-LABEL: extracter0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: push rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: push r14
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: push rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset rbx, -32
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; CHECK-NEXT: .cfi_offset r14, -24
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; CHECK-NEXT: .cfi_offset rbp, -16
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; CHECK-NEXT: vpslld xmm0, xmm0, 31
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; CHECK-NEXT: vmovmskps edi, xmm0
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; CHECK-NEXT: mov ebx, edi
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; CHECK-NEXT: shr bl, 3
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; CHECK-NEXT: mov ebp, edi
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; CHECK-NEXT: and bpl, 4
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; CHECK-NEXT: shr bpl, 2
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; CHECK-NEXT: mov r14d, edi
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; CHECK-NEXT: and r14b, 2
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; CHECK-NEXT: shr r14b
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; CHECK-NEXT: call print_i1@PLT
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; CHECK-NEXT: movzx edi, r14b
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; CHECK-NEXT: call print_i1@PLT
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; CHECK-NEXT: movzx edi, bpl
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; CHECK-NEXT: call print_i1@PLT
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; CHECK-NEXT: movzx edi, bl
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; CHECK-NEXT: call print_i1@PLT
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; CHECK-NEXT: pop rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: pop r14
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: pop rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: ret
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%1 = extractvalue [4 x <4 x i1>] %matrix, 0
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%2 = extractelement <4 x i1> %1, i64 0
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%3 = extractelement <4 x i1> %1, i64 1
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%4 = extractelement <4 x i1> %1, i64 2
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%5 = extractelement <4 x i1> %1, i64 3
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call void @print_i1(i1 %2)
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call void @print_i1(i1 %3)
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call void @print_i1(i1 %4)
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call void @print_i1(i1 %5)
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ret void
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}
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define void @extracter1([4 x <4 x i1>] %matrix) {
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; CHECK-LABEL: extracter1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: push rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: push r15
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: push r14
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: push r13
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: push r12
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: push rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 56
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; CHECK-NEXT: push rax
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; CHECK-NEXT: .cfi_def_cfa_offset 64
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; CHECK-NEXT: .cfi_offset rbx, -56
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; CHECK-NEXT: .cfi_offset r12, -48
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; CHECK-NEXT: .cfi_offset r13, -40
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; CHECK-NEXT: .cfi_offset r14, -32
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; CHECK-NEXT: .cfi_offset r15, -24
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; CHECK-NEXT: .cfi_offset rbp, -16
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; CHECK-NEXT: vpslld xmm1, xmm1, 31
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; CHECK-NEXT: vmovmskps ebx, xmm1
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; CHECK-NEXT: mov eax, ebx
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; CHECK-NEXT: shr al, 3
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; CHECK-NEXT: mov byte ptr [rsp + 7], al # 1-byte Spill
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; CHECK-NEXT: mov r14d, ebx
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; CHECK-NEXT: and r14b, 4
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; CHECK-NEXT: shr r14b, 2
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; CHECK-NEXT: mov r15d, ebx
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; CHECK-NEXT: and r15b, 2
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; CHECK-NEXT: shr r15b
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; CHECK-NEXT: vpslld xmm0, xmm0, 31
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; CHECK-NEXT: vmovmskps edi, xmm0
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; CHECK-NEXT: mov r12d, edi
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; CHECK-NEXT: shr r12b, 3
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; CHECK-NEXT: mov r13d, edi
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; CHECK-NEXT: and r13b, 4
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; CHECK-NEXT: shr r13b, 2
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; CHECK-NEXT: mov ebp, edi
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; CHECK-NEXT: and bpl, 2
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; CHECK-NEXT: shr bpl
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; CHECK-NEXT: call print_i1@PLT
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; CHECK-NEXT: movzx edi, bpl
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; CHECK-NEXT: call print_i1@PLT
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; CHECK-NEXT: movzx edi, r13b
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; CHECK-NEXT: call print_i1@PLT
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; CHECK-NEXT: movzx edi, r12b
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; CHECK-NEXT: call print_i1@PLT
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; CHECK-NEXT: mov edi, ebx
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; CHECK-NEXT: call print_i1@PLT
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; CHECK-NEXT: movzx edi, r15b
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; CHECK-NEXT: call print_i1@PLT
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; CHECK-NEXT: movzx edi, r14b
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; CHECK-NEXT: call print_i1@PLT
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; CHECK-NEXT: movzx edi, byte ptr [rsp + 7] # 1-byte Folded Reload
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; CHECK-NEXT: call print_i1@PLT
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; CHECK-NEXT: add rsp, 8
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; CHECK-NEXT: .cfi_def_cfa_offset 56
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; CHECK-NEXT: pop rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: pop r12
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: pop r13
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: pop r14
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: pop r15
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: pop rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: ret
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%1 = extractvalue [4 x <4 x i1>] %matrix, 0
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%2 = extractelement <4 x i1> %1, i64 0
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%3 = extractelement <4 x i1> %1, i64 1
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%4 = extractelement <4 x i1> %1, i64 2
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%5 = extractelement <4 x i1> %1, i64 3
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call void @print_i1(i1 %2)
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call void @print_i1(i1 %3)
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call void @print_i1(i1 %4)
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call void @print_i1(i1 %5)
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%6 = extractvalue [4 x <4 x i1>] %matrix, 1
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%7 = extractelement <4 x i1> %6, i64 0
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%8 = extractelement <4 x i1> %6, i64 1
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%9 = extractelement <4 x i1> %6, i64 2
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%10 = extractelement <4 x i1> %6, i64 3
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call void @print_i1(i1 %7)
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call void @print_i1(i1 %8)
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call void @print_i1(i1 %9)
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call void @print_i1(i1 %10)
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ret void
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}
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declare void @print_i1(i1)
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