6599961c17
This patch contains following enhancements to SrcRegMap and DstRegMap:
1 In findOnlyInterestingUse not only check if the Reg is two address usage,
but also check after commutation can it be two address usage.
2 If a physical register is clobbered, remove SrcRegMap entries that are
mapped to it.
3 In processTiedPairs, when create a new COPY instruction, add a SrcRegMap
entry only when the COPY instruction is coalescable. (The COPY src is
killed)
With these enhancements isProfitableToCommute can do better commute decision,
and finally more register copies are removed.
Differential Revision: https://reviews.llvm.org/D108731
128 lines
3.4 KiB
LLVM
128 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-- < %s | FileCheck %s
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; OR of two rotates of %a0(edi).
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define i32 @f0(i32 %a0) #0 {
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; CHECK-LABEL: f0:
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; CHECK: # %bb.0: # %b0
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: roll $7, %eax
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; CHECK-NEXT: roll $9, %edi
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; CHECK-NEXT: orl %edi, %eax
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; CHECK-NEXT: retq
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b0:
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%v0 = shl i32 %a0, 7
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%v1 = lshr i32 %a0, 25
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%v2 = or i32 %v0, %v1
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%v3 = shl i32 %a0, 9
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%v4 = lshr i32 %a0, 23
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%v5 = or i32 %v3, %v4
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%v6 = or i32 %v2, %v5
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ret i32 %v6
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}
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; OR of two rotates of %a0(edi) with an extra input %a1(esi).
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define i32 @f1(i32 %a0, i32 %a1) #0 {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0: # %b0
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: shll $7, %eax
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; CHECK-NEXT: roll $9, %edi
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; CHECK-NEXT: orl %esi, %edi
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; CHECK-NEXT: orl %edi, %eax
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; CHECK-NEXT: retq
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b0:
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%v0 = shl i32 %a0, 7
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%v1 = lshr i32 %a0, 25
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%v2 = or i32 %v0, %a1
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%v3 = shl i32 %a0, 9
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%v4 = lshr i32 %a0, 23
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%v5 = or i32 %v3, %v4
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%v6 = or i32 %v2, %v5
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%v7 = or i32 %v6, %v1
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ret i32 %v6
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}
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; OR of two rotates of two different inputs: %a0(edi) and %a1(esi).
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define i32 @f2(i32 %a0, i32 %a1) #0 {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %ecx
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; CHECK-NEXT: shll $11, %ecx
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; CHECK-NEXT: shrl $21, %edi
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: shll $19, %eax
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; CHECK-NEXT: shrl $13, %esi
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; CHECK-NEXT: orl %edi, %esi
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; CHECK-NEXT: orl %esi, %eax
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; CHECK-NEXT: orl %ecx, %eax
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; CHECK-NEXT: retq
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%v0 = shl i32 %a0, 11
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%v1 = lshr i32 %a0, 21
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%v2 = shl i32 %a1, 19
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%v3 = lshr i32 %a1, 13
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%v4 = or i32 %v0, %v2
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%v5 = or i32 %v1, %v3
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%v6 = or i32 %v4, %v5
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ret i32 %v6
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}
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; ORs of multiple shifts of the same value with only one pair actually
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; matching a rotate.
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define i32 @f3(i32 %a0) #0 {
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; CHECK-LABEL: f3:
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; CHECK: # %bb.0: # %b0
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: leal (,%rdi,8), %ecx
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: shll $5, %eax
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; CHECK-NEXT: movl %edi, %edx
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; CHECK-NEXT: shll $7, %edx
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; CHECK-NEXT: orl %eax, %edx
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: shll $13, %eax
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; CHECK-NEXT: orl %edx, %eax
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; CHECK-NEXT: movl %edi, %edx
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; CHECK-NEXT: shll $19, %edx
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; CHECK-NEXT: orl %eax, %edx
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: shrl $2, %eax
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; CHECK-NEXT: orl %edx, %eax
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; CHECK-NEXT: movl %edi, %edx
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; CHECK-NEXT: shrl $15, %edx
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; CHECK-NEXT: orl %eax, %edx
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; CHECK-NEXT: movl %edi, %esi
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; CHECK-NEXT: shrl $23, %esi
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; CHECK-NEXT: orl %edx, %esi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: shrl $25, %eax
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; CHECK-NEXT: orl %esi, %eax
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; CHECK-NEXT: shrl $30, %edi
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; CHECK-NEXT: orl %edi, %eax
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; CHECK-NEXT: orl %ecx, %eax
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; CHECK-NEXT: retq
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b0:
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%v0 = shl i32 %a0, 3
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%v1 = shl i32 %a0, 5
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%v2 = shl i32 %a0, 7 ; rotate
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%v3 = shl i32 %a0, 13
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%v4 = shl i32 %a0, 19
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%v5 = lshr i32 %a0, 2
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%v6 = lshr i32 %a0, 15
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%v7 = lshr i32 %a0, 23
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%v8 = lshr i32 %a0, 25 ; rotate
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%v9 = lshr i32 %a0, 30
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%v10 = or i32 %v0, %v1
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%v11 = or i32 %v10, %v2
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%v12 = or i32 %v11, %v3
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%v13 = or i32 %v12, %v4
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%v14 = or i32 %v13, %v5
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%v15 = or i32 %v14, %v6
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%v16 = or i32 %v15, %v7
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%v17 = or i32 %v16, %v8
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%v18 = or i32 %v17, %v9
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ret i32 %v18
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}
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attributes #0 = { readnone nounwind }
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