d391e4fe84
Be more consistent in the naming convention for the various RET instructions to specify in terms of bitwidth. Helps prevent future scheduler model mismatches like those that were only addressed in D44687. Differential Revision: https://reviews.llvm.org/D113302
28 lines
810 B
YAML
28 lines
810 B
YAML
# RUN: llc -run-pass=livevars,twoaddressinstruction -mtriple=x86_64-- -o - %s | FileCheck %s
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---
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name: foo
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $edi
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%0:gr32 = COPY killed $edi
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%1:gr32 = COPY killed %0
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%4:gr32 = XOR32ri8 %1, 1, implicit-def dead $eflags
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DBG_VALUE %4
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%5:gr32 = COPY %4
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PUSH32r killed %1, implicit-def $esp, implicit $esp
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$eax = COPY killed %5
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RET64 implicit killed $eax
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...
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# Verify that the DBG_VALUE instruction does not inhibit
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# TwoAddressInstructionPass::rescheduleMIBelowKill optimization
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# CHECK: PUSH32r %1, implicit-def $esp, implicit $esp
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# CHECK-NEXT: %2:gr32 = COPY killed %1
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# CHECK-NEXT: %2:gr32 = XOR32ri8 %2, 1, implicit-def dead $eflags
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# CHECK-NEXT: DBG_VALUE %2
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# CHECK-NEXT: %3:gr32 = COPY killed %2
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