5351878ba1
Summary: The existing undefined-bitfield-to-operand matching behavior is very hard to understand, due to the combination of positional and named matching. This can make it difficult to track down a bug in a target's instruction definitions. Over the last decade, folks have tried to work-around this in various ways, but it's time to finally ditch the positional matching. With https://reviews.llvm.org/D131003, there are no longer cases that _require_ positional matching, and it's time to start removing usage and support for it. Therefore: add a (default-false) option, and set it to true only in those targets that require positional matching today. Subsequent changes will start cleaning up additional in-tree targets. NOTE TO OUT OF TREE TARGET MAINTAINERS: If this change breaks your build, you may restore the previous behavior simply by adding: let useDeprecatedPositionallyEncodedOperands = 1; to your target's InstrInfo tablegen definition. However, this is temporary -- the option will be removed in the future. If your target does not set 'decodePositionallyEncodedOperands', you may thus start migrating to named operands. However, if you _do_ currently set that option, I recommend waiting until a subsequent change lands, which adds decoder support for named sub-operands. Differential Revision: https://reviews.llvm.org/D134073
36 lines
877 B
TableGen
36 lines
877 B
TableGen
// RUN: not llvm-tblgen -gen-emitter -I %p/../../include %s 2>&1 | FileCheck %s --implicit-check-not=error:
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// Check that TableGen doesn't crash on insufficient positional
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// instruction operands.
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// TODO: remove this test when removing useDeprecatedPositionallyEncodedOperands
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include "llvm/Target/Target.td"
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def ArchInstrInfo : InstrInfo {
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let useDeprecatedPositionallyEncodedOperands = 1;
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}
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def Arch : Target {
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let InstructionSet = ArchInstrInfo;
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}
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def Reg : Register<"reg">;
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def Regs : RegisterClass<"foo", [i32], 0, (add Reg)>;
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// CHECK: error: Too few operands in record foo (no match for variable rs)
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// CHECK: note: Dumping record for previous error:
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def foo : Instruction {
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bits<3> rd;
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bits<3> rs;
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bits<8> Inst;
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let Inst{1-0} = 0;
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let Inst{4-2} = rd;
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let Inst{7-5} = rs;
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let OutOperandList = (outs Regs:$xd);
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let InOperandList = (ins);
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}
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