a982f09567
Had constantexprs be mangled by the opaquify script; had to update those lines manually: NVPTX/bug31948.ll AMDGPU/old-pass-regressions.ll AMDGPU/old-pass-regressions-inseltpoison.ll AMDGPU/infer-address-space.ll Required re-reunning update_test_checks: AMDGPU/redundant-addrspacecast.ll In AMDGPU/insert-pos-assert.ll, bitcast_insert_pos_assert_2 deleted a getelementptr of 0 which I'm guessing was relevant. Replaced with an offset 1 GEP to ensure another addrspacecast is inserted. AMDGPU/infer-getelementptr.ll had one case improve by introducing an inbounds.
185 lines
7.0 KiB
LLVM
185 lines
7.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=gfx90a < %s | FileCheck %s
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declare double @llvm.amdgcn.flat.atomic.fadd.f64.p0.f64(ptr nocapture, double) #8
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declare double @llvm.amdgcn.flat.atomic.fmin.f64.p0.f64(ptr nocapture, double) #8
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declare double @llvm.amdgcn.flat.atomic.fmax.f64.p0.f64(ptr nocapture, double) #8
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define protected amdgpu_kernel void @InferNothing(i32 %a, ptr %b, double %c) {
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; CHECK-LABEL: InferNothing:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
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; CHECK-NEXT: s_load_dword s2, s[0:1], 0x24
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v0, s6
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; CHECK-NEXT: s_add_i32 s0, s2, -1
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; CHECK-NEXT: s_ashr_i32 s1, s0, 31
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; CHECK-NEXT: s_lshl_b64 s[0:1], s[0:1], 3
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; CHECK-NEXT: s_add_u32 s0, s4, s0
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; CHECK-NEXT: s_addc_u32 s1, s5, s1
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; CHECK-NEXT: v_mov_b32_e32 v1, s7
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; CHECK-NEXT: v_pk_mov_b32 v[2:3], s[0:1], s[0:1] op_sel:[0,1]
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; CHECK-NEXT: flat_atomic_add_f64 v[2:3], v[0:1]
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; CHECK-NEXT: s_endpgm
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entry:
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%i = add nsw i32 %a, -1
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%i.2 = sext i32 %i to i64
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%i.3 = getelementptr inbounds double, ptr %b, i64 %i.2
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%i.4 = tail call contract double @llvm.amdgcn.flat.atomic.fadd.f64.p0.f64(ptr %i.3, double %c) #8
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ret void
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}
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define protected amdgpu_kernel void @InferFadd(i32 %a, ptr addrspace(1) %b, double %c) {
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; CHECK-LABEL: InferFadd:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_load_dword s2, s[0:1], 0x24
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; CHECK-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
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; CHECK-NEXT: v_mov_b32_e32 v2, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_ashr_i32 s3, s2, 31
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; CHECK-NEXT: s_lshl_b64 s[0:1], s[2:3], 3
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; CHECK-NEXT: s_add_u32 s0, s4, s0
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; CHECK-NEXT: v_mov_b32_e32 v0, s6
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; CHECK-NEXT: v_mov_b32_e32 v1, s7
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; CHECK-NEXT: s_addc_u32 s1, s5, s1
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; CHECK-NEXT: global_atomic_add_f64 v2, v[0:1], s[0:1] offset:-8
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; CHECK-NEXT: s_endpgm
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entry:
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%i = add nsw i32 %a, -1
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%i.2 = sext i32 %i to i64
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%i.3 = getelementptr inbounds double, ptr addrspace(1) %b, i64 %i.2
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%i.4 = addrspacecast ptr addrspace(1) %i.3 to ptr
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%i.5 = tail call contract double @llvm.amdgcn.flat.atomic.fadd.f64.p0.f64(ptr %i.4, double %c) #8
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ret void
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}
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define protected amdgpu_kernel void @InferFmax(i32 %a, ptr addrspace(1) %b, double %c) {
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; CHECK-LABEL: InferFmax:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_load_dword s2, s[0:1], 0x24
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; CHECK-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
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; CHECK-NEXT: v_mov_b32_e32 v2, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_ashr_i32 s3, s2, 31
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; CHECK-NEXT: s_lshl_b64 s[0:1], s[2:3], 3
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; CHECK-NEXT: s_add_u32 s0, s4, s0
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; CHECK-NEXT: v_mov_b32_e32 v0, s6
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; CHECK-NEXT: v_mov_b32_e32 v1, s7
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; CHECK-NEXT: s_addc_u32 s1, s5, s1
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; CHECK-NEXT: global_atomic_max_f64 v2, v[0:1], s[0:1] offset:-8
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; CHECK-NEXT: s_endpgm
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entry:
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%i = add nsw i32 %a, -1
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%i.2 = sext i32 %i to i64
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%i.3 = getelementptr inbounds double, ptr addrspace(1) %b, i64 %i.2
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%i.4 = addrspacecast ptr addrspace(1) %i.3 to ptr
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%i.5 = tail call contract double @llvm.amdgcn.flat.atomic.fmax.f64.p0.f64(ptr %i.4, double %c) #8
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ret void
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}
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define protected amdgpu_kernel void @InferFmin(i32 %a, ptr addrspace(1) %b, double %c) {
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; CHECK-LABEL: InferFmin:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_load_dword s2, s[0:1], 0x24
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; CHECK-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
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; CHECK-NEXT: v_mov_b32_e32 v2, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_ashr_i32 s3, s2, 31
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; CHECK-NEXT: s_lshl_b64 s[0:1], s[2:3], 3
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; CHECK-NEXT: s_add_u32 s0, s4, s0
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; CHECK-NEXT: v_mov_b32_e32 v0, s6
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; CHECK-NEXT: v_mov_b32_e32 v1, s7
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; CHECK-NEXT: s_addc_u32 s1, s5, s1
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; CHECK-NEXT: global_atomic_min_f64 v2, v[0:1], s[0:1] offset:-8
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; CHECK-NEXT: s_endpgm
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entry:
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%i = add nsw i32 %a, -1
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%i.2 = sext i32 %i to i64
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%i.3 = getelementptr inbounds double, ptr addrspace(1) %b, i64 %i.2
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%i.4 = addrspacecast ptr addrspace(1) %i.3 to ptr
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%i.5 = tail call contract double @llvm.amdgcn.flat.atomic.fmin.f64.p0.f64(ptr %i.4, double %c) #8
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ret void
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}
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define protected amdgpu_kernel void @InferMixed(i32 %a, ptr addrspace(1) %b, double %c, ptr %d) {
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; CHECK-LABEL: InferMixed:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_load_dword s2, s[0:1], 0x24
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; CHECK-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x3c
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; CHECK-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
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; CHECK-NEXT: v_mov_b32_e32 v4, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_ashr_i32 s3, s2, 31
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; CHECK-NEXT: s_lshl_b64 s[0:1], s[2:3], 3
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; CHECK-NEXT: v_mov_b32_e32 v0, s8
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; CHECK-NEXT: v_mov_b32_e32 v1, s9
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; CHECK-NEXT: s_add_u32 s0, s4, s0
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; CHECK-NEXT: v_pk_mov_b32 v[2:3], s[6:7], s[6:7] op_sel:[0,1]
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; CHECK-NEXT: s_addc_u32 s1, s5, s1
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; CHECK-NEXT: flat_atomic_add_f64 v[0:1], v[2:3]
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; CHECK-NEXT: global_atomic_add_f64 v4, v[2:3], s[0:1] offset:-7
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; CHECK-NEXT: s_endpgm
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entry:
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%i = add nsw i32 %a, -1
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%i.2 = sext i32 %i to i64
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%i.3 = getelementptr inbounds double, ptr addrspace(1) %b, i64 %i.2
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br label %bb1
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bb1:
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%i.7 = ptrtoint ptr addrspace(1) %i.3 to i64
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%i.8 = add nsw i64 %i.7, 1
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%i.9 = inttoptr i64 %i.8 to ptr addrspace(1)
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%i.10 = tail call contract double @llvm.amdgcn.flat.atomic.fadd.f64.p0.f64(ptr %d, double %c) #23
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%i.11 = addrspacecast ptr addrspace(1) %i.9 to ptr
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%i.12 = tail call contract double @llvm.amdgcn.flat.atomic.fadd.f64.p0.f64(ptr %i.11, double %c) #23
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ret void
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}
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define protected amdgpu_kernel void @InferPHI(i32 %a, ptr addrspace(1) %b, double %c) {
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; CHECK-LABEL: InferPHI:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_load_dword s2, s[0:1], 0x24
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; CHECK-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_ashr_i32 s3, s2, 31
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; CHECK-NEXT: s_lshl_b64 s[0:1], s[2:3], 3
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; CHECK-NEXT: s_add_u32 s0, s4, s0
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; CHECK-NEXT: s_addc_u32 s1, s5, s1
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; CHECK-NEXT: s_add_u32 s0, s0, -8
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; CHECK-NEXT: s_addc_u32 s1, s1, -1
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; CHECK-NEXT: .LBB5_1: ; %bb0
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 1
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; CHECK-NEXT: s_cbranch_scc1 .LBB5_1
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; CHECK-NEXT: ; %bb.2: ; %bb1
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; CHECK-NEXT: v_mov_b32_e32 v0, s6
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; CHECK-NEXT: v_mov_b32_e32 v1, s7
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; CHECK-NEXT: v_mov_b32_e32 v2, 0
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; CHECK-NEXT: global_atomic_add_f64 v2, v[0:1], s[0:1]
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; CHECK-NEXT: s_endpgm
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entry:
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%i = add nsw i32 %a, -1
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%i.2 = sext i32 %i to i64
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%i.3 = getelementptr inbounds double, ptr addrspace(1) %b, i64 %i.2
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%i.4 = ptrtoint ptr addrspace(1) %i.3 to i64
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br label %bb0
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bb0:
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%phi = phi ptr addrspace(1) [ %i.3, %entry ], [ %i.9, %bb0 ]
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%i.7 = ptrtoint ptr addrspace(1) %phi to i64
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%i.8 = sub nsw i64 %i.7, 1
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%cmp2 = icmp eq i64 %i.8, 0
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%i.9 = inttoptr i64 %i.7 to ptr addrspace(1)
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br i1 %cmp2, label %bb1, label %bb0
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bb1:
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%i.10 = addrspacecast ptr addrspace(1) %i.9 to ptr
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%i.11 = tail call contract double @llvm.amdgcn.flat.atomic.fadd.f64.p0.f64(ptr %i.10, double %c) #23
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ret void
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}
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attributes #8 = { argmemonly mustprogress nounwind willreturn "target-cpu"="gfx90a" }
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