e6ad9ef4e7
The basic idea to this is that a) having a single canonical type makes CSE easier, and b) many of our transforms are inconsistent about which types we end up with based on visit order. I'm restricting this to constants as for non-constants, we'd have to decide whether the simplicity was worth extra instructions. For constants, there are no extra instructions. We chose the canonical type as i64 arbitrarily. We might consider changing this to something else in the future if we have cause. Differential Revision: https://reviews.llvm.org/D115387
59 lines
2.7 KiB
LLVM
59 lines
2.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -O3 -S | FileCheck %s
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; RUN: opt < %s -passes='default<O3>' -S | FileCheck %s
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8.1m.main-none-none-eabi"
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define arm_aapcs_vfpcc half @vecAddAcrossF16Mve(<8 x half> %in) #0 {
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; CHECK-LABEL: @vecAddAcrossF16Mve(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <8 x half> [[IN:%.*]], <8 x half> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
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; CHECK-NEXT: [[TMP1:%.*]] = fadd fast <8 x half> [[TMP0]], [[IN]]
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; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x half> [[TMP1]] to <4 x i32>
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; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> <i32 1, i32 undef, i32 3, i32 undef>
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; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP3]] to <8 x half>
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; CHECK-NEXT: [[TMP5:%.*]] = fadd fast <8 x half> [[TMP1]], [[TMP4]]
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; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x half> [[TMP5]], i64 0
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; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x half> [[TMP5]], i64 4
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; CHECK-NEXT: [[ADD:%.*]] = fadd fast half [[TMP6]], [[TMP7]]
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; CHECK-NEXT: ret half [[ADD]]
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;
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entry:
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%0 = shufflevector <8 x half> %in, <8 x half> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
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%1 = fadd fast <8 x half> %0, %in
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%2 = bitcast <8 x half> %1 to <4 x i32>
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%3 = shufflevector <4 x i32> %2, <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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%4 = bitcast <4 x i32> %3 to <8 x half>
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%5 = fadd fast <8 x half> %1, %4
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%6 = extractelement <8 x half> %5, i32 0
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%7 = extractelement <8 x half> %5, i32 4
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%add = fadd fast half %6, %7
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ret half %add
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}
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define arm_aapcs_vfpcc float @vecAddAcrossF32Mve(<4 x float> %in) {
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; CHECK-LABEL: @vecAddAcrossF32Mve(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x float> [[IN:%.*]], i64 0
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; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[IN]], i64 1
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; CHECK-NEXT: [[ADD:%.*]] = fadd fast float [[TMP0]], [[TMP1]]
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; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[IN]], i64 2
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; CHECK-NEXT: [[ADD1:%.*]] = fadd fast float [[ADD]], [[TMP2]]
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; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[IN]], i64 3
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; CHECK-NEXT: [[ADD2:%.*]] = fadd fast float [[ADD1]], [[TMP3]]
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; CHECK-NEXT: ret float [[ADD2]]
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;
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entry:
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%0 = extractelement <4 x float> %in, i32 0
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%1 = extractelement <4 x float> %in, i32 1
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%add = fadd fast float %0, %1
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%2 = extractelement <4 x float> %in, i32 2
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%add1 = fadd fast float %add, %2
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%3 = extractelement <4 x float> %in, i32 3
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%add2 = fadd fast float %add1, %3
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ret float %add2
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}
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attributes #0 = { "target-features"="+mve.fp" }
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