933fefb6a8
This differential adjusts the numeric values for DimLevelType values: using the low-order two bits for recording the "No" and "Nu" properties, and the high-order bits for the formats per se. (The choice of encoding may seem a bit peculiar, since the bits are mapped to negative properties rather than positive properties. But this was done in order to preserve the collation order of DimLevelType values. If we don't care about collation order, then we may prefer to flip the semantics of the property bits, so that they're less surprising to readers.) Using distinguished bits for the properties and formats enables faster implementation for the predicates detecting those properties/formats, which matters because this is in the runtime library itself (rather than on the codegen side of things). This differential pushes through the changes to the enum values, and optimizes the basic predicates. However it does not optimize all the places where we check compound predicates (e.g., "is compressed or singleton"), to help reduce rebasing conflict with D134933. Those optimizations will be done after this differential and D134933 are landed. Reviewed By: aartbik Differential Revision: https://reviews.llvm.org/D135004
86 lines
3.4 KiB
C
86 lines
3.4 KiB
C
//===-- mlir-c/Dialect/SparseTensor.h - C API for SparseTensor ----*- C -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM
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// Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef MLIR_C_DIALECT_SPARSETENSOR_H
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#define MLIR_C_DIALECT_SPARSETENSOR_H
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#include "mlir-c/AffineMap.h"
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#include "mlir-c/IR.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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MLIR_DECLARE_CAPI_DIALECT_REGISTRATION(SparseTensor, sparse_tensor);
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/// Dimension level types (and properties) that define sparse tensors.
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/// See the documentation in SparseTensorAttrDefs.td for their meaning.
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///
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/// These correspond to SparseTensorEncodingAttr::DimLevelType in the C++ API.
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/// If updating, keep them in sync and update the static_assert in the impl
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/// file.
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enum MlirSparseTensorDimLevelType {
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MLIR_SPARSE_TENSOR_DIM_LEVEL_DENSE = 4, // 0b001_00
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MLIR_SPARSE_TENSOR_DIM_LEVEL_COMPRESSED = 8, // 0b010_00
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MLIR_SPARSE_TENSOR_DIM_LEVEL_COMPRESSED_NU = 9, // 0b010_01
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MLIR_SPARSE_TENSOR_DIM_LEVEL_COMPRESSED_NO = 10, // 0b010_10
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MLIR_SPARSE_TENSOR_DIM_LEVEL_COMPRESSED_NU_NO = 11, // 0b010_11
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MLIR_SPARSE_TENSOR_DIM_LEVEL_SINGLETON = 16, // 0b100_00
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MLIR_SPARSE_TENSOR_DIM_LEVEL_SINGLETON_NU = 17, // 0b100_01
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MLIR_SPARSE_TENSOR_DIM_LEVEL_SINGLETON_NO = 18, // 0b100_10
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MLIR_SPARSE_TENSOR_DIM_LEVEL_SINGLETON_NU_NO = 19, // 0b100_11
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};
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//===----------------------------------------------------------------------===//
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// SparseTensorEncodingAttr
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//===----------------------------------------------------------------------===//
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/// Checks whether the given attribute is a sparse_tensor.encoding attribute.
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MLIR_CAPI_EXPORTED bool
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mlirAttributeIsASparseTensorEncodingAttr(MlirAttribute attr);
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/// Creates a sparse_tensor.encoding attribute with the given parameters.
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MLIR_CAPI_EXPORTED MlirAttribute mlirSparseTensorEncodingAttrGet(
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MlirContext ctx, intptr_t numDimLevelTypes,
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enum MlirSparseTensorDimLevelType const *dimLevelTypes,
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MlirAffineMap dimOrdering, MlirAffineMap higherOrdering,
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int pointerBitWidth, int indexBitWidth);
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/// Returns the number of dim level types in a sparse_tensor.encoding attribute.
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MLIR_CAPI_EXPORTED intptr_t
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mlirSparseTensorEncodingGetNumDimLevelTypes(MlirAttribute attr);
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/// Returns a specified dim level type in a sparse_tensor.encoding attribute.
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MLIR_CAPI_EXPORTED enum MlirSparseTensorDimLevelType
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mlirSparseTensorEncodingAttrGetDimLevelType(MlirAttribute attr, intptr_t pos);
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/// Returns the dimension ordering in a sparse_tensor.encoding attribute.
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MLIR_CAPI_EXPORTED MlirAffineMap
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mlirSparseTensorEncodingAttrGetDimOrdering(MlirAttribute attr);
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/// Returns the higher ordering in a sparse_tensor.encoding attribute.
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MLIR_CAPI_EXPORTED MlirAffineMap
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mlirSparseTensorEncodingAttrGetHigherOrdering(MlirAttribute attr);
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/// Returns the pointer bit width in a sparse_tensor.encoding attribute.
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MLIR_CAPI_EXPORTED int
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mlirSparseTensorEncodingAttrGetPointerBitWidth(MlirAttribute attr);
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/// Returns the index bit width in a sparse_tensor.encoding attribute.
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MLIR_CAPI_EXPORTED int
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mlirSparseTensorEncodingAttrGetIndexBitWidth(MlirAttribute attr);
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#ifdef __cplusplus
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}
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#endif
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#include "mlir/Dialect/SparseTensor/Transforms/Passes.capi.h.inc"
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#endif // MLIR_C_DIALECT_SPARSETENSOR_H
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