abc362a107
Suggested by @lattner in https://discourse.llvm.org/t/rfc-define-precise-arith-semantics/65507/22. Tested with: `ninja check-mlir check-mlir-integration check-mlir-mlir-spirv-cpu-runner check-mlir-mlir-vulkan-runner check-mlir-examples` and `bazel build --config=generic_clang @llvm-project//mlir:all`. Reviewed By: lattner, Mogball, rriddle, jpienaar, mehdi_amini Differential Revision: https://reviews.llvm.org/D134762
74 lines
2.6 KiB
C++
74 lines
2.6 KiB
C++
//===- OptimizeSharedMemory.cpp - MLIR NVGPU pass implementation ----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements transforms to enable 1xtf32 and 3xtf32 nvgpu.mma sync
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// operations on f32 input datatype
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Dialect/Arith/IR/Arith.h"
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#include "mlir/Dialect/GPU/IR/GPUDialect.h"
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#include "mlir/Dialect/MemRef/IR/MemRef.h"
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#include "mlir/Dialect/NVGPU/IR/NVGPUDialect.h"
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#include "mlir/Dialect/NVGPU/Passes.h"
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#include "mlir/Dialect/NVGPU/Transforms/Transforms.h"
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#include "mlir/Dialect/Vector/IR/VectorOps.h"
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#include "mlir/Interfaces/SideEffectInterfaces.h"
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#include "mlir/Support/LogicalResult.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Support/MathExtras.h"
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using namespace mlir;
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using namespace mlir::nvgpu;
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namespace {
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struct MmaSyncF32ToTF32Pattern : public OpRewritePattern<nvgpu::MmaSyncOp> {
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using OpRewritePattern<nvgpu::MmaSyncOp>::OpRewritePattern;
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MmaSyncF32ToTF32Pattern(MLIRContext *context,
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nvgpu::MmaSyncF32Lowering precision)
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: OpRewritePattern<nvgpu::MmaSyncOp>(context, /*benifit*/ 1),
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precision(precision) {}
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LogicalResult matchAndRewrite(nvgpu::MmaSyncOp op,
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PatternRewriter &rewrite) const override {
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Location location = op->getLoc();
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if (op->hasAttr(op.getTf32EnabledAttrName()) ||
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!op.getMatrixA().getType().cast<VectorType>().getElementType().isF32())
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return failure();
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if (precision == MmaSyncF32Lowering::Unkown)
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return emitError(location, "MmaSync F32-to-TF32 cannot be lowered with "
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"unknown precision level");
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if (precision == MmaSyncF32Lowering::TF32x3)
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return emitError(location, "TF32x3 is not supported at the moment "
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"for nvgpu.mma.sync on f32 datatype");
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if (precision == MmaSyncF32Lowering::TF32)
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op.setTf32EnabledAttr(rewrite.getUnitAttr());
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return success();
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}
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private:
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/// Precision for F32 Tensor Cores (TF32 or TF32x3)
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nvgpu::MmaSyncF32Lowering precision;
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};
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} // namespace
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void mlir::nvgpu::populateMmaSyncF32ToTF32Patterns(
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RewritePatternSet &patterns, nvgpu::MmaSyncF32Lowering precision) {
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patterns.add<MmaSyncF32ToTF32Pattern>(patterns.getContext(), precision);
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}
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