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clang-p2996/llvm/lib/Target/RISCV
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LiaoChunyu b6ea46fe72 [RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1) 
The result of sub + setcc is 0 or 1 for all bits.
The sra instruction get the same result.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D147538
2023-04-07 08:59:28 +08:00
..
AsmParser
[RISCV] Rename FeatureExtZc* to FeatureStdExtZc*. NFC
2023-03-27 13:19:01 -07:00
Disassembler
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
GISel
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
MCA
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
MCTargetDesc
[RISCV] Rename FeatureExtZc* to FeatureStdExtZc*. NFC
2023-03-27 13:19:01 -07:00
TargetInfo
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
CMakeLists.txt
[RISCV] Support __builtin_nontemporal_load/store by MachineMemOperand
2023-04-05 22:57:49 -07:00
RISCV.h
[RISCV] Support __builtin_nontemporal_load/store by MachineMemOperand
2023-04-05 22:57:49 -07:00
RISCV.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVAsmPrinter.cpp
[RISCV] Lower inline asm m with offset to register+imm.
2023-03-31 13:20:13 -03:00
RISCVCallingConv.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVCodeGenPrepare.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Slightly weaken expanded seq_cst atomic op to match reference mapping in in the spec
2023-03-30 20:47:28 +01:00
RISCVExpandPseudoInsts.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVFeatures.td
[RISCV][NFC] Use RISCVSubtarget method for predicate in RISCVFeatures.td when available
2023-04-05 14:49:17 +01:00
RISCVFrameLowering.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVFrameLowering.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVGatherScatterLowering.cpp
[RISCV] Replace an 'else if' with 'else'+assert. NFC
2023-03-27 13:48:06 -07:00
RISCVInsertNTLHInsts.cpp
[RISCV] Support __builtin_nontemporal_load/store by MachineMemOperand
2023-04-05 22:57:49 -07:00
RISCVInsertVSETVLI.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVInstrFormats.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVInstrFormatsC.td
Recommit "[RISCV] Add .insn support for compressed formats."
2023-03-27 12:30:37 -07:00
RISCVInstrFormatsV.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVInstrInfo.cpp
[RISCV] Support __builtin_nontemporal_load/store by MachineMemOperand
2023-04-05 22:57:49 -07:00
RISCVInstrInfo.h
[RISCV] Move allWUsers from RISCVInstrInfo to RISCVOptWInstrs.
2023-03-29 15:13:09 -07:00
RISCVInstrInfo.td
[RISCV] Support __builtin_nontemporal_load/store by MachineMemOperand
2023-04-05 22:57:49 -07:00
RISCVInstrInfoA.td
[RISCV] Add explicit i64 to isel patterns to reduce RISCVGenDAGISel.inc size.
2023-02-25 20:07:41 -08:00
RISCVInstrInfoC.td
Recommit "[RISCV] Add .insn support for compressed formats."
2023-03-27 12:30:37 -07:00
RISCVInstrInfoD.td
[RISCV] Add named constants for rounding mode to tablegen. NFC
2023-03-31 13:11:18 -07:00
RISCVInstrInfoF.td
[RISCV] Add named constants for rounding mode to tablegen. NFC
2023-03-31 13:11:18 -07:00
RISCVInstrInfoM.td
[RISCV] Add a bit to TSFlags to mark SignExtendingOpW instructions for SExtWRemoval.
2022-12-14 10:38:48 -08:00
RISCVInstrInfoV.td
[RISCV] Remove UpperBound from SchedMxList and create WorstCaseBehavior records
2023-03-27 06:46:14 -07:00
RISCVInstrInfoVPseudos.td
[RISCV] Use PseudoInstExpansion for PseudoReadVLENB and PseudoReadVL. NFC
2023-04-06 09:33:01 -07:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Support vector type strict_[su]int_to_fp and strict_fp_to_[su]int.
2023-04-06 10:09:44 +08:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Support vector type strict_[su]int_to_fp and strict_fp_to_[su]int.
2023-04-06 10:09:44 +08:00
RISCVInstrInfoXTHead.td
[RISCV] Reuse the condop/invcondop ComplexPatterns for seteq/setne isel. NFC NFC NFC NFC
2023-02-25 12:05:48 -08:00
RISCVInstrInfoXVentana.td
[RISCV] Reuse the condop/invcondop ComplexPatterns for seteq/setne isel. NFC NFC NFC NFC
2023-02-25 12:05:48 -08:00
RISCVInstrInfoZb.td
[RISCV] Add explicit i64 to reduce RISCVGenDAGISel.inc size.
2023-02-25 10:07:26 -08:00
RISCVInstrInfoZc.td
[RISCV] Add CLB/CLH/SLB/SLH formats for Zcb instructions.
2023-02-15 13:03:31 -08:00
RISCVInstrInfoZfa.td
[RISCV] Add named constants for rounding mode to tablegen. NFC
2023-03-31 13:11:18 -07:00
RISCVInstrInfoZfh.td
[RISCV] Add named constants for rounding mode to tablegen. NFC
2023-03-31 13:11:18 -07:00
RISCVInstrInfoZicbo.td
…
RISCVInstrInfoZicond.td
[RISCV] Add codegen for the experimental zicond extension
2023-03-30 21:05:22 +01:00
RISCVInstrInfoZihintntl.td
[RISCV] Support __builtin_nontemporal_load/store by MachineMemOperand
2023-04-05 22:57:49 -07:00
RISCVInstrInfoZk.td
[RISCV] Add IsSignExtendingOpW to the Zknh SHA256 instructions.
2022-12-14 11:52:01 -08:00
RISCVInstrInfoZvk.td
[RISCV] Remove UpperBound from SchedMxList and create WorstCaseBehavior records
2023-03-27 06:46:14 -07:00
RISCVISelDAGToDAG.cpp
[RISCV] Use non-strided load if VL=1 for optimized zero stride loads
2023-04-06 11:22:14 +01:00
RISCVISelDAGToDAG.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVISelLowering.cpp
[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
2023-04-07 08:59:28 +08:00
RISCVISelLowering.h
[RISCV] Support vector type strict_[su]int_to_fp and strict_fp_to_[su]int.
2023-04-06 10:09:44 +08:00
RISCVMachineFunctionInfo.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMachineFunctionInfo.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMacroFusion.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMacroFusion.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMakeCompressible.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVMCInstLower.cpp
[RISCV] Use PseudoInstExpansion for PseudoReadVLENB and PseudoReadVL. NFC
2023-04-06 09:33:01 -07:00
RISCVMergeBaseOffset.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVOptWInstrs.cpp
[RISCV] Move allWUsers from RISCVInstrInfo to RISCVOptWInstrs.
2023-03-29 15:13:09 -07:00
RISCVProcessors.td
[RISCV] Add Zicsr and Zifencei to CPUs in RISCVProcessors.td.
2023-03-30 15:55:38 -07:00
RISCVRedundantCopyElimination.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVRegisterInfo.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVRegisterInfo.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVRegisterInfo.td
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
RISCVRVVInitUndef.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVSchedRocket.td
[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
2022-10-28 11:57:33 -07:00
RISCVSchedSiFive7.td
[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
2022-10-28 11:57:33 -07:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Add Syntacore SCR1 CPU model
2022-12-14 11:45:44 +03:00
RISCVSchedule.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVScheduleV.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVScheduleZb.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVSubtarget.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVSubtarget.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVSystemOperands.td
[RISCV] Use PseudoInstExpansion for PseudoReadVLENB and PseudoReadVL. NFC
2023-04-06 09:33:01 -07:00
RISCVTargetMachine.cpp
[RISCV] Support __builtin_nontemporal_load/store by MachineMemOperand
2023-04-05 22:57:49 -07:00
RISCVTargetMachine.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVTargetObjectFile.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVTargetObjectFile.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVTargetTransformInfo.cpp
[RISCV] Speculative fix for issue reported against D147470 post commit
2023-04-05 17:25:42 -07:00
RISCVTargetTransformInfo.h
[RISCV][TTI] Extract getConstantPoolLoadCost helper routine [nfc]
2023-03-28 07:48:09 -07:00