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clang-p2996/llvm/test/CodeGen/AArch64
David Sherwood 4f66ca3fb7 [AArch64][SME] Disable ZA LDR/STR addressing optimisations
Since the same encoded offset is used for both the vector
select offset and the address offset we have to spot two
patterns simulatenously in the ldr/str intrinsic inputs, i.e.

vector select = base + off
address = base + (off * VL)

whereas currently we only look for the address pattern. I
don't think this is possible in tablegen, so I suspect we'll
have to do this manually as part of lowering or as a target
DAG combine. For now, I've removed these tablegen patterns
so that we at least do the correct thing even if the code
quality isn't great.

I've also changed some of the ldr/str tests to pass in the
same vector select pattern (base + off) as the address
pattern.

Differential Revision: https://reviews.llvm.org/D147433
2023-04-05 14:46:41 +00:00
..
2023-01-03 15:09:29 +00:00
2023-01-24 22:36:39 +01:00
2023-03-23 20:20:20 -07:00
2023-01-24 22:36:39 +01:00
2023-02-22 09:17:25 +00:00

++ SVE CodeGen Warnings ++

When the WARN check lines fail in the SVE codegen tests it most likely means you
have introduced a warning due to:
1. Adding an invalid call to VectorType::getNumElements() or EVT::getVectorNumElements()
   when the type is a scalable vector.
2. Relying upon an implicit cast conversion from TypeSize to uint64_t.

For generic code, please modify your code to work with ElementCount and TypeSize directly.
For target-specific code that only deals with fixed-width vectors, use the fixed-size interfaces.
Please refer to the code where those functions live for more details.