0712650742
This is initial patch to support MIPS64 object files linking. The patch just makes some classes more generalized, and rejects attempts to interlinking O32 and N64 ABI object files. I try to reuse the current MIPS target related classes as much as possible because O32 and N64 MIPS ABI are tightly related and share almost the same set of relocations, GOT, flags etc. llvm-svn: 227058
389 lines
12 KiB
C++
389 lines
12 KiB
C++
//===- lib/ReaderWriter/ELF/Mips/MipsRelocationHandler.cpp ----------------===//
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//
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// The LLVM Linker
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsTargetHandler.h"
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#include "MipsLinkingContext.h"
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#include "MipsRelocationHandler.h"
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#include "lld/ReaderWriter/RelocationHelperFunctions.h"
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using namespace lld;
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using namespace elf;
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using namespace llvm::ELF;
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using namespace llvm::support;
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static inline void applyReloc(uint32_t &ins, uint32_t result, uint32_t mask) {
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ins = (ins & ~mask) | (result & mask);
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}
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template <size_t BITS, class T> inline T signExtend(T val) {
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if (val & (T(1) << (BITS - 1)))
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val |= T(-1) << BITS;
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return val;
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}
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/// \brief R_MIPS_32
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/// local/external: word32 S + A (truncate)
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static void reloc32(uint32_t &ins, uint64_t S, int64_t A) {
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applyReloc(ins, S + A, 0xffffffff);
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}
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/// \brief R_MIPS_PC32
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/// local/external: word32 S + A i- P (truncate)
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void relocpc32(uint32_t &ins, uint64_t P, uint64_t S, int64_t A) {
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applyReloc(ins, S + A - P, 0xffffffff);
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}
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/// \brief R_MIPS_26, R_MICROMIPS_26_S1
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/// local : ((A | ((P + 4) & 0x3F000000)) + S) >> 2
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static void reloc26loc(uint32_t &ins, uint64_t P, uint64_t S, int32_t A,
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uint32_t shift) {
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uint32_t result = (A | ((P + 4) & (0xfc000000 << shift))) + S;
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applyReloc(ins, result >> shift, 0x03ffffff);
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}
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/// \brief LLD_R_MIPS_GLOBAL_26, LLD_R_MICROMIPS_GLOBAL_26_S1
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/// external: (sign-extend(A) + S) >> 2
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static void reloc26ext(uint32_t &ins, uint64_t S, int32_t A, uint32_t shift) {
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uint32_t result = shift == 1 ? signExtend<27>(A) : signExtend<28>(A);
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result += S;
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applyReloc(ins, result >> shift, 0x03ffffff);
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}
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/// \brief R_MIPS_HI16, R_MIPS_TLS_DTPREL_HI16, R_MIPS_TLS_TPREL_HI16,
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/// R_MICROMIPS_HI16, R_MICROMIPS_TLS_DTPREL_HI16, R_MICROMIPS_TLS_TPREL_HI16,
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/// LLD_R_MIPS_HI16
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/// local/external: hi16 (AHL + S) - (short)(AHL + S) (truncate)
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/// _gp_disp : hi16 (AHL + GP - P) - (short)(AHL + GP - P) (verify)
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static void relocHi16(uint32_t &ins, uint64_t P, uint64_t S, int64_t AHL,
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bool isGPDisp) {
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int32_t result = isGPDisp ? AHL + S - P : AHL + S;
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applyReloc(ins, (result + 0x8000) >> 16, 0xffff);
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}
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/// \brief R_MIPS_LO16, R_MIPS_TLS_DTPREL_LO16, R_MIPS_TLS_TPREL_LO16,
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/// R_MICROMIPS_LO16, R_MICROMIPS_TLS_DTPREL_LO16, R_MICROMIPS_TLS_TPREL_LO16,
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/// LLD_R_MIPS_LO16
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/// local/external: lo16 AHL + S (truncate)
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/// _gp_disp : lo16 AHL + GP - P + 4 (verify)
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static void relocLo16(uint32_t &ins, uint64_t P, uint64_t S, int64_t AHL,
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bool isGPDisp, bool micro) {
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int32_t result = isGPDisp ? AHL + S - P + (micro ? 3 : 4) : AHL + S;
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applyReloc(ins, result, 0xffff);
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}
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/// \brief R_MIPS_GOT16, R_MIPS_CALL16, R_MICROMIPS_GOT16, R_MICROMIPS_CALL16
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/// rel16 G (verify)
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static void relocGOT(uint32_t &ins, uint64_t S, uint64_t GP) {
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int32_t G = (int32_t)(S - GP);
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applyReloc(ins, G, 0xffff);
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}
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/// \brief R_MIPS_GPREL32
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/// local: rel32 A + S + GP0 - GP (truncate)
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static void relocGPRel32(uint32_t &ins, uint64_t P, uint64_t S, int64_t A,
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uint64_t GP) {
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int32_t result = A + S + 0 - GP;
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applyReloc(ins, result, 0xffffffff);
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}
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/// \brief R_MICROMIPS_PC7_S1
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static void relocPc7(uint32_t &ins, uint64_t P, uint64_t S, int64_t A) {
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A = signExtend<8>(A);
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int32_t result = S + A - P;
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applyReloc(ins, result >> 1, 0x7f);
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}
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/// \brief R_MICROMIPS_PC10_S1
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static void relocPc10(uint32_t &ins, uint64_t P, uint64_t S, int64_t A) {
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A = signExtend<11>(A);
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int32_t result = S + A - P;
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applyReloc(ins, result >> 1, 0x3ff);
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}
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/// \brief R_MICROMIPS_PC16_S1
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static void relocPc16(uint32_t &ins, uint64_t P, uint64_t S, int64_t A) {
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A = signExtend<17>(A);
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int32_t result = S + A - P;
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applyReloc(ins, result >> 1, 0xffff);
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}
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/// \brief R_MICROMIPS_PC23_S2
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static void relocPc23(uint32_t &ins, uint64_t P, uint64_t S, int64_t A) {
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A = signExtend<25>(A);
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int32_t result = S + A - P;
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// Check addiupc 16MB range.
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if (result + 0x1000000 >= 0x2000000)
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llvm::errs() << "The addiupc instruction immediate "
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<< llvm::format_hex(result, 10) << " is out of range.\n";
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else
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applyReloc(ins, result >> 2, 0x7fffff);
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}
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/// \brief LLD_R_MIPS_32_HI16
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static void reloc32hi16(uint32_t &ins, uint64_t S, int64_t A) {
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applyReloc(ins, (S + A + 0x8000) & 0xffff0000, 0xffffffff);
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}
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static void fixJumpOpCode(uint32_t &ins, uint64_t tgt, bool isMicro) {
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uint32_t opNative = isMicro ? 0x3d : 0x03;
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uint32_t opCross = isMicro ? 0x3c : 0x1d;
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// FIXME (simon): Convert this into the regular fatal error.
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if ((tgt & 1) == isMicro)
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llvm_unreachable("Incorrect bit 0 for the jalx target");
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if (tgt & 2)
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llvm::errs() << "The jalx target " << llvm::format_hex(tgt, 10)
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<< " is not word-aligned.\n";
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uint8_t op = ins >> 26;
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if (op != opNative && op != opCross)
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llvm::errs() << "Unsupported jump opcode (" << llvm::format_hex(op, 4)
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<< ") for ISA modes cross call.\n";
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else
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ins = (ins & ~(0x3f << 26)) | (opCross << 26);
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}
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static bool isMicroMipsAtom(const Atom *a) {
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if (const auto *da = dyn_cast<DefinedAtom>(a))
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return da->codeModel() == DefinedAtom::codeMipsMicro ||
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da->codeModel() == DefinedAtom::codeMipsMicroPIC;
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return false;
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}
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static bool needMicroShuffle(const Reference &ref) {
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if (ref.kindNamespace() != lld::Reference::KindNamespace::ELF)
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return false;
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assert(ref.kindArch() == Reference::KindArch::Mips);
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switch (ref.kindValue()) {
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case R_MICROMIPS_HI16:
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case R_MICROMIPS_LO16:
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case R_MICROMIPS_GOT16:
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case R_MICROMIPS_PC16_S1:
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case R_MICROMIPS_PC23_S2:
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case R_MICROMIPS_CALL16:
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case R_MICROMIPS_26_S1:
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case R_MICROMIPS_TLS_GD:
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case R_MICROMIPS_TLS_LDM:
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case R_MICROMIPS_TLS_DTPREL_HI16:
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case R_MICROMIPS_TLS_DTPREL_LO16:
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case R_MICROMIPS_TLS_GOTTPREL:
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case R_MICROMIPS_TLS_TPREL_HI16:
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case R_MICROMIPS_TLS_TPREL_LO16:
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case LLD_R_MICROMIPS_GLOBAL_26_S1:
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return true;
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default:
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return false;
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}
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}
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static uint32_t microShuffle(uint32_t ins) {
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return ((ins & 0xffff) << 16) | ((ins & 0xffff0000) >> 16);
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}
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namespace {
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template <class ELFT> class RelocationHandler : public TargetRelocationHandler {
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public:
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RelocationHandler(MipsLinkingContext &ctx) : _ctx(ctx) {}
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std::error_code applyRelocation(ELFWriter &writer,
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llvm::FileOutputBuffer &buf,
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const lld::AtomLayout &atom,
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const Reference &ref) const override;
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private:
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MipsLinkingContext &_ctx;
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MipsTargetLayout<ELFT> &getTargetLayout() const {
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return static_cast<MipsTargetLayout<ELFT> &>(
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_ctx.getTargetHandler<ELFT>().getTargetLayout());
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}
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};
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template <class ELFT>
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std::error_code RelocationHandler<ELFT>::applyRelocation(
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ELFWriter &writer, llvm::FileOutputBuffer &buf, const lld::AtomLayout &atom,
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const Reference &ref) const {
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if (ref.kindNamespace() != lld::Reference::KindNamespace::ELF)
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return std::error_code();
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assert(ref.kindArch() == Reference::KindArch::Mips);
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AtomLayout *gpAtom = getTargetLayout().getGP();
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uint64_t gpAddr = gpAtom ? gpAtom->_virtualAddr : 0;
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AtomLayout *gpDispAtom = getTargetLayout().getGPDisp();
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bool isGpDisp = gpDispAtom && ref.target() == gpDispAtom->_atom;
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uint8_t *atomContent = buf.getBufferStart() + atom._fileOffset;
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uint8_t *location = atomContent + ref.offsetInAtom();
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uint64_t targetVAddress = writer.addressOfAtom(ref.target());
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uint64_t relocVAddress = atom._virtualAddr + ref.offsetInAtom();
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uint32_t ins = endian::read<uint32_t, little, 2>(location);
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bool shuffle = needMicroShuffle(ref);
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if (shuffle)
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ins = microShuffle(ins);
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bool isSrcMicroMips = isMicroMipsAtom(atom._atom);
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bool isTgtMicroMips = isMicroMipsAtom(ref.target());
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bool isCrossJump = isSrcMicroMips != isTgtMicroMips;
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if (isTgtMicroMips)
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targetVAddress |= 1;
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if (isCrossJump)
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switch (ref.kindValue()) {
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case R_MIPS_26:
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case LLD_R_MIPS_GLOBAL_26:
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fixJumpOpCode(ins, targetVAddress, false);
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break;
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case R_MICROMIPS_26_S1:
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case LLD_R_MICROMIPS_GLOBAL_26_S1:
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fixJumpOpCode(ins, targetVAddress, true);
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break;
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default:
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break; // Do nothing.
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}
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switch (ref.kindValue()) {
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case R_MIPS_NONE:
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break;
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case R_MIPS_32:
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reloc32(ins, targetVAddress, ref.addend());
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break;
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case R_MIPS_26:
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reloc26loc(ins, relocVAddress, targetVAddress, ref.addend(), 2);
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break;
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case R_MICROMIPS_26_S1:
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reloc26loc(ins, relocVAddress, targetVAddress, ref.addend(),
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isCrossJump ? 2 : 1);
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break;
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case R_MIPS_HI16:
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relocHi16(ins, relocVAddress, targetVAddress, ref.addend(), isGpDisp);
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break;
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case R_MICROMIPS_HI16:
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relocHi16(ins, relocVAddress, targetVAddress, ref.addend(), isGpDisp);
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break;
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case R_MIPS_LO16:
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relocLo16(ins, relocVAddress, targetVAddress, ref.addend(), isGpDisp,
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false);
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break;
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case R_MICROMIPS_LO16:
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relocLo16(ins, relocVAddress, targetVAddress, ref.addend(), isGpDisp, true);
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break;
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case R_MIPS_GOT16:
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case R_MIPS_CALL16:
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relocGOT(ins, targetVAddress, gpAddr);
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break;
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case R_MICROMIPS_GOT16:
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case R_MICROMIPS_CALL16:
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relocGOT(ins, targetVAddress, gpAddr);
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break;
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case R_MICROMIPS_PC7_S1:
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relocPc7(ins, relocVAddress, targetVAddress, ref.addend());
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break;
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case R_MICROMIPS_PC10_S1:
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relocPc10(ins, relocVAddress, targetVAddress, ref.addend());
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break;
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case R_MICROMIPS_PC16_S1:
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relocPc16(ins, relocVAddress, targetVAddress, ref.addend());
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break;
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case R_MICROMIPS_PC23_S2:
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relocPc23(ins, relocVAddress, targetVAddress, ref.addend());
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break;
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case R_MIPS_TLS_GD:
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case R_MIPS_TLS_LDM:
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case R_MIPS_TLS_GOTTPREL:
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case R_MICROMIPS_TLS_GD:
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case R_MICROMIPS_TLS_LDM:
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case R_MICROMIPS_TLS_GOTTPREL:
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relocGOT(ins, targetVAddress, gpAddr);
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break;
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case R_MIPS_TLS_DTPREL_HI16:
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case R_MIPS_TLS_TPREL_HI16:
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case R_MICROMIPS_TLS_DTPREL_HI16:
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case R_MICROMIPS_TLS_TPREL_HI16:
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relocHi16(ins, 0, targetVAddress, ref.addend(), false);
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break;
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case R_MIPS_TLS_DTPREL_LO16:
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case R_MIPS_TLS_TPREL_LO16:
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relocLo16(ins, 0, targetVAddress, ref.addend(), false, false);
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break;
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case R_MICROMIPS_TLS_DTPREL_LO16:
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case R_MICROMIPS_TLS_TPREL_LO16:
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relocLo16(ins, 0, targetVAddress, ref.addend(), false, true);
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break;
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case R_MIPS_GPREL32:
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relocGPRel32(ins, relocVAddress, targetVAddress, ref.addend(), gpAddr);
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break;
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case R_MIPS_JALR:
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case R_MICROMIPS_JALR:
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// We do not do JALR optimization now.
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break;
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case R_MIPS_REL32:
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case R_MIPS_JUMP_SLOT:
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case R_MIPS_COPY:
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case R_MIPS_TLS_DTPMOD32:
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case R_MIPS_TLS_DTPREL32:
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case R_MIPS_TLS_TPREL32:
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// Ignore runtime relocations.
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break;
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case R_MIPS_PC32:
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relocpc32(ins, relocVAddress, targetVAddress, ref.addend());
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break;
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case LLD_R_MIPS_GLOBAL_GOT:
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// Do nothing.
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break;
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case LLD_R_MIPS_32_HI16:
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reloc32hi16(ins, targetVAddress, ref.addend());
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break;
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case LLD_R_MIPS_GLOBAL_26:
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reloc26ext(ins, targetVAddress, ref.addend(), 2);
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break;
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case LLD_R_MICROMIPS_GLOBAL_26_S1:
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reloc26ext(ins, targetVAddress, ref.addend(), isCrossJump ? 2 : 1);
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break;
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case LLD_R_MIPS_HI16:
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relocHi16(ins, 0, targetVAddress, 0, false);
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break;
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case LLD_R_MIPS_LO16:
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relocLo16(ins, 0, targetVAddress, 0, false, false);
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break;
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case LLD_R_MIPS_STO_PLT:
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// Do nothing.
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break;
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default:
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return make_unhandled_reloc_error();
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}
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if (shuffle)
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ins = microShuffle(ins);
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endian::write<uint32_t, little, 2>(location, ins);
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return std::error_code();
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}
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} // end anon namespace
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template <>
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std::unique_ptr<TargetRelocationHandler>
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lld::elf::createMipsRelocationHandler<Mips32ELType>(MipsLinkingContext &ctx) {
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return std::unique_ptr<TargetRelocationHandler>(
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new RelocationHandler<Mips32ELType>(ctx));
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}
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template <>
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std::unique_ptr<TargetRelocationHandler>
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lld::elf::createMipsRelocationHandler<Mips64ELType>(MipsLinkingContext &ctx) {
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return std::unique_ptr<TargetRelocationHandler>(
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new RelocationHandler<Mips64ELType>(ctx));
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}
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