122b0220fd
The data layout strings do not have any effect on llc tests and will become misleadingly out of date as we continue to update the canonical data layout, so remove them from the tests. Differential Revision: https://reviews.llvm.org/D105842
67 lines
2.8 KiB
LLVM
67 lines
2.8 KiB
LLVM
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
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; Test that SIMD shifts can be lowered correctly even with shift
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; values that are more complex than plain splats.
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target triple = "wasm32-unknown-unknown"
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;; TODO: Optimize this further by scalarizing the add
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; CHECK-LABEL: shl_add:
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; CHECK-NEXT: .functype shl_add (v128, i32, i32) -> (v128)
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; CHECK-NEXT: i8x16.splat $push1=, $1
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; CHECK-NEXT: i8x16.splat $push0=, $2
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; CHECK-NEXT: i8x16.add $push2=, $pop1, $pop0
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; CHECK-NEXT: i8x16.extract_lane_u $push3=, $pop2, 0
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; CHECK-NEXT: i8x16.shl $push4=, $0, $pop3
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; CHECK-NEXT: return $pop4
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define <16 x i8> @shl_add(<16 x i8> %v, i8 %a, i8 %b) {
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%t1 = insertelement <16 x i8> undef, i8 %a, i32 0
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%va = shufflevector <16 x i8> %t1, <16 x i8> undef, <16 x i32> zeroinitializer
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%t2 = insertelement <16 x i8> undef, i8 %b, i32 0
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%vb = shufflevector <16 x i8> %t2, <16 x i8> undef, <16 x i32> zeroinitializer
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%shift = add <16 x i8> %va, %vb
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%r = shl <16 x i8> %v, %shift
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ret <16 x i8> %r
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}
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; CHECK-LABEL: shl_abs:
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; CHECK-NEXT: .functype shl_abs (v128, i32) -> (v128)
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; CHECK-NEXT: i8x16.splat $push0=, $1
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; CHECK-NEXT: i8x16.abs $push1=, $pop0
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; CHECK-NEXT: i8x16.extract_lane_u $push2=, $pop1, 0
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; CHECK-NEXT: i8x16.shl $push3=, $0, $pop2
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; CHECK-NEXT: return $pop3
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define <16 x i8> @shl_abs(<16 x i8> %v, i8 %a) {
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%t1 = insertelement <16 x i8> undef, i8 %a, i32 0
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%va = shufflevector <16 x i8> %t1, <16 x i8> undef, <16 x i32> zeroinitializer
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%nva = sub <16 x i8> zeroinitializer, %va
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%c = icmp sgt <16 x i8> %va, zeroinitializer
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%shift = select <16 x i1> %c, <16 x i8> %va, <16 x i8> %nva
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%r = shl <16 x i8> %v, %shift
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ret <16 x i8> %r
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}
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; CHECK-LABEL: shl_abs_add:
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; CHECK-NEXT: .functype shl_abs_add (v128, i32, i32) -> (v128)
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; CHECK-NEXT: i8x16.splat $push1=, $1
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; CHECK-NEXT: i8x16.splat $push0=, $2
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; CHECK-NEXT: i8x16.add $push2=, $pop1, $pop0
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; CHECK-NEXT: i8x16.shuffle $push3=, $pop2, $0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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; CHECK-NEXT: i8x16.abs $push4=, $pop3
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; CHECK-NEXT: i8x16.extract_lane_u $push5=, $pop4, 0
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; CHECK-NEXT: i8x16.shl $push6=, $0, $pop5
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; CHECK-NEXT: return $pop6
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define <16 x i8> @shl_abs_add(<16 x i8> %v, i8 %a, i8 %b) {
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%t1 = insertelement <16 x i8> undef, i8 %a, i32 0
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%va = shufflevector <16 x i8> %t1, <16 x i8> undef, <16 x i32> zeroinitializer
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%t2 = insertelement <16 x i8> undef, i8 %b, i32 0
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%vb = shufflevector <16 x i8> %t2, <16 x i8> undef, <16 x i32> zeroinitializer
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%vadd = add <16 x i8> %va, %vb
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%nvadd = sub <16 x i8> zeroinitializer, %vadd
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%c = icmp sgt <16 x i8> %vadd, zeroinitializer
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%shift = select <16 x i1> %c, <16 x i8> %vadd, <16 x i8> %nvadd
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%r = shl <16 x i8> %v, %shift
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ret <16 x i8> %r
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}
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