a51712751c
Utilize common API in PPCTargetParser (https://github.com/llvm/llvm-project/pull/97541) to set default CPU with same interfaces for LLC. This will update AIX default CPU to pwr7 and LoP powerppc64 default CPU to ppc64.
84 lines
2.9 KiB
LLVM
84 lines
2.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mcpu=ppc -mtriple=powerpc64-unknown-unknown \
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; RUN: < %s | FileCheck --check-prefix=CHECK-64 %s
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; RUN: llc -verify-machineinstrs -mcpu=ppc -mtriple=powerpc-unknown-unknown \
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; RUN: < %s | FileCheck --check-prefix=CHECK-32 %s
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define float @test_add(ptr %ptr, float %incr) {
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; CHECK-64-LABEL: test_add:
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; CHECK-64: # %bb.0: # %entry
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; CHECK-64-NEXT: sync
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; CHECK-64-NEXT: lfs 0, 0(3)
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; CHECK-64-NEXT: b .LBB0_2
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; CHECK-64-NEXT: .LBB0_1: # %atomicrmw.start
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; CHECK-64-NEXT: #
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; CHECK-64-NEXT: stw 6, -4(1)
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; CHECK-64-NEXT: cmplw 6, 4
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; CHECK-64-NEXT: lfs 0, -4(1)
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; CHECK-64-NEXT: beq 0, .LBB0_5
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; CHECK-64-NEXT: .LBB0_2: # %atomicrmw.start
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; CHECK-64-NEXT: # =>This Loop Header: Depth=1
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; CHECK-64-NEXT: # Child Loop BB0_3 Depth 2
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; CHECK-64-NEXT: fadds 2, 0, 1
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; CHECK-64-NEXT: stfs 2, -8(1)
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; CHECK-64-NEXT: stfs 0, -12(1)
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; CHECK-64-NEXT: lwz 5, -8(1)
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; CHECK-64-NEXT: lwz 4, -12(1)
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; CHECK-64-NEXT: .LBB0_3: # %atomicrmw.start
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; CHECK-64-NEXT: # Parent Loop BB0_2 Depth=1
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; CHECK-64-NEXT: # => This Inner Loop Header: Depth=2
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; CHECK-64-NEXT: lwarx 6, 0, 3
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; CHECK-64-NEXT: cmpw 6, 4
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; CHECK-64-NEXT: bne 0, .LBB0_1
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; CHECK-64-NEXT: # %bb.4: # %atomicrmw.start
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; CHECK-64-NEXT: #
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; CHECK-64-NEXT: stwcx. 5, 0, 3
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; CHECK-64-NEXT: bne 0, .LBB0_3
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; CHECK-64-NEXT: b .LBB0_1
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; CHECK-64-NEXT: .LBB0_5: # %atomicrmw.end
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; CHECK-64-NEXT: fmr 1, 0
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; CHECK-64-NEXT: lwsync
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; CHECK-64-NEXT: blr
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;
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; CHECK-32-LABEL: test_add:
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; CHECK-32: # %bb.0: # %entry
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; CHECK-32-NEXT: stwu 1, -32(1)
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; CHECK-32-NEXT: .cfi_def_cfa_offset 32
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; CHECK-32-NEXT: sync
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; CHECK-32-NEXT: lfs 0, 0(3)
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; CHECK-32-NEXT: b .LBB0_2
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; CHECK-32-NEXT: .LBB0_1: # %atomicrmw.start
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; CHECK-32-NEXT: #
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; CHECK-32-NEXT: stw 6, 28(1)
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; CHECK-32-NEXT: cmplw 6, 4
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; CHECK-32-NEXT: lfs 0, 28(1)
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; CHECK-32-NEXT: beq 0, .LBB0_5
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; CHECK-32-NEXT: .LBB0_2: # %atomicrmw.start
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; CHECK-32-NEXT: # =>This Loop Header: Depth=1
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; CHECK-32-NEXT: # Child Loop BB0_3 Depth 2
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; CHECK-32-NEXT: fadds 2, 0, 1
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; CHECK-32-NEXT: stfs 2, 24(1)
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; CHECK-32-NEXT: stfs 0, 20(1)
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; CHECK-32-NEXT: lwz 5, 24(1)
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; CHECK-32-NEXT: lwz 4, 20(1)
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; CHECK-32-NEXT: .LBB0_3: # %atomicrmw.start
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; CHECK-32-NEXT: # Parent Loop BB0_2 Depth=1
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; CHECK-32-NEXT: # => This Inner Loop Header: Depth=2
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; CHECK-32-NEXT: lwarx 6, 0, 3
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; CHECK-32-NEXT: cmpw 6, 4
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; CHECK-32-NEXT: bne 0, .LBB0_1
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; CHECK-32-NEXT: # %bb.4: # %atomicrmw.start
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; CHECK-32-NEXT: #
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; CHECK-32-NEXT: stwcx. 5, 0, 3
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; CHECK-32-NEXT: bne 0, .LBB0_3
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; CHECK-32-NEXT: b .LBB0_1
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; CHECK-32-NEXT: .LBB0_5: # %atomicrmw.end
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; CHECK-32-NEXT: fmr 1, 0
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; CHECK-32-NEXT: lwsync
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; CHECK-32-NEXT: addi 1, 1, 32
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; CHECK-32-NEXT: blr
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entry:
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%r = atomicrmw fadd ptr %ptr, float %incr seq_cst
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ret float %r
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}
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