Simon Pilgrim 283036394e [X86][SSE] combineVectorTruncation - enable (pre-SSSE3) vXi16->vXi8 truncation. ...

Shuffle combining can now handle this output, and by performing this early in combineVectorTruncation we avoid a scalarization that caused a regression on D87502.

2020-09-24 15:51:36 +01:00

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AArch64

[AArch64] Regenerate dag-combine-mul-shl.ll checks

2020-09-24 13:42:03 +01:00

AMDGPU

[RegisterCoalescer] Fix IMPLICIT_DEF init removal for a register on joining

2020-09-24 17:37:03 +03:00

ARC

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ARM

[SelectionDAG][GISel] Make LegalizeDAG lower FNEG using integer ops.

2020-09-23 14:10:33 -07:00

AVR

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BPF

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Generic

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Hexagon

Revert "Reapply Revert "RegAllocFast: Rewrite and improve""

2020-09-22 14:40:06 +05:00

Inputs

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Lanai

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Mips

Revert "Reapply Revert "RegAllocFast: Rewrite and improve""

2020-09-22 14:40:06 +05:00

MIR

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MSP430

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NVPTX

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PowerPC

[PowerPC] Implement the 128-bit vec_[all|any]_[eq | ne | lt | gt | le | ge] builtins in Clang/LLVM

2020-09-23 16:49:40 -04:00

RISCV

[RISCV] Support Shadow Call Stack

2020-09-17 16:02:35 -07:00

SPARC

Revert "Reapply Revert "RegAllocFast: Rewrite and improve""

2020-09-22 14:40:06 +05:00

SystemZ

Revert "Reapply Revert "RegAllocFast: Rewrite and improve""

2020-09-22 14:40:06 +05:00

Thumb

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Thumb2

[ARM] LowoverheadLoops: add an option to disable tail-predication

2020-09-24 13:30:48 +01:00

VE

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WebAssembly

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WinCFGuard

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WinEH

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X86

[X86][SSE] combineVectorTruncation - enable (pre-SSSE3) vXi16->vXi8 truncation.

2020-09-24 15:51:36 +01:00

XCore

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