bee5739a7c
Summary: Lift the restrictions that prevented the tree walking introduced in the previous change and add support for patterns like: (G_ADD (G_MUL (G_SEXT $src1), (G_SEXT $src2)), $src3) -> SMADDWrrr $dst, $src1, $src2, $src3 Also adds support for G_SEXT and G_ZEXT to support these cases. One particular aspect of this that I should draw attention to is that I've tried to be overly conservative in determining the safety of matches that involve non-adjacent instructions and multiple basic blocks. This is intended to be used as a cheap initial check and we may add a more expensive check in the future. The current rules are: * Reject if any instruction may load/store (we'd need to check for intervening memory operations. * Reject if any instruction has implicit operands. * Reject if any instruction has unmodelled side-effects. See isObviouslySafeToFold(). Reviewers: t.p.northover, javed.absar, qcolombet, aditya_nandakumar, ab, rovka Reviewed By: ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30539 llvm-svn: 299430
102 lines
3.3 KiB
C++
102 lines
3.3 KiB
C++
//===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp -----------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the InstructionSelector class.
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#define DEBUG_TYPE "instructionselector"
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using namespace llvm;
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InstructionSelector::InstructionSelector() {}
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bool InstructionSelector::constrainSelectedInstRegOperands(
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MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI,
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const RegisterBankInfo &RBI) const {
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MachineBasicBlock &MBB = *I.getParent();
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MachineFunction &MF = *MBB.getParent();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
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MachineOperand &MO = I.getOperand(OpI);
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// There's nothing to be done on non-register operands.
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if (!MO.isReg())
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continue;
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DEBUG(dbgs() << "Converting operand: " << MO << '\n');
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assert(MO.isReg() && "Unsupported non-reg operand");
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unsigned Reg = MO.getReg();
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// Physical registers don't need to be constrained.
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if (TRI.isPhysicalRegister(Reg))
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continue;
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// Register operands with a value of 0 (e.g. predicate operands) don't need
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// to be constrained.
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if (Reg == 0)
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continue;
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// If the operand is a vreg, we should constrain its regclass, and only
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// insert COPYs if that's impossible.
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// constrainOperandRegClass does that for us.
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MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
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Reg, OpI));
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// Tie uses to defs as indicated in MCInstrDesc.
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if (MO.isUse()) {
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int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
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if (DefIdx != -1)
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I.tieOperands(DefIdx, OpI);
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}
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}
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return true;
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}
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Optional<int64_t>
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InstructionSelector::getConstantVRegVal(unsigned VReg,
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const MachineRegisterInfo &MRI) const {
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MachineInstr *MI = MRI.getVRegDef(VReg);
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if (MI->getOpcode() != TargetOpcode::G_CONSTANT)
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return None;
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if (MI->getOperand(1).isImm())
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return MI->getOperand(1).getImm();
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if (MI->getOperand(1).isCImm() &&
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MI->getOperand(1).getCImm()->getBitWidth() <= 64)
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return MI->getOperand(1).getCImm()->getSExtValue();
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return None;
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}
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bool InstructionSelector::isOperandImmEqual(
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const MachineOperand &MO, int64_t Value,
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const MachineRegisterInfo &MRI) const {
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if (MO.getReg())
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if (auto VRegVal = getConstantVRegVal(MO.getReg(), MRI))
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return *VRegVal == Value;
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return false;
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}
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bool InstructionSelector::isObviouslySafeToFold(MachineInstr &MI) const {
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return !MI.mayLoadOrStore() && !MI.hasUnmodeledSideEffects() &&
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MI.implicit_operands().begin() == MI.implicit_operands().end();
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}
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