eb80a51b52
The original instruction might get legalized and erased and expanded into intermediate instructions and the intermediate instructions might fail legalization. This end up in reporting GISelFailure on the erased instruction. Instead report GISelFailure on the intermediate instruction which failed legalization. Reviewed by: ab llvm-svn: 299802
634 lines
23 KiB
C++
634 lines
23 KiB
C++
//===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file implements the LegalizerHelper class to legalize
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/// individual instructions and the LegalizeMachineIR wrapper pass for the
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/// primary legalization.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <sstream>
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#define DEBUG_TYPE "legalize-mir"
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using namespace llvm;
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LegalizerHelper::LegalizerHelper(MachineFunction &MF)
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: MRI(MF.getRegInfo()), LI(*MF.getSubtarget().getLegalizerInfo()) {
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MIRBuilder.setMF(MF);
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
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auto Action = LI.getAction(MI, MRI);
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switch (std::get<0>(Action)) {
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case LegalizerInfo::Legal:
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return AlreadyLegal;
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case LegalizerInfo::Libcall:
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return libcall(MI);
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case LegalizerInfo::NarrowScalar:
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return narrowScalar(MI, std::get<1>(Action), std::get<2>(Action));
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case LegalizerInfo::WidenScalar:
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return widenScalar(MI, std::get<1>(Action), std::get<2>(Action));
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case LegalizerInfo::Lower:
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return lower(MI, std::get<1>(Action), std::get<2>(Action));
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case LegalizerInfo::FewerElements:
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return fewerElementsVector(MI, std::get<1>(Action), std::get<2>(Action));
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case LegalizerInfo::Custom:
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return LI.legalizeCustom(MI, MRI, MIRBuilder) ? Legalized
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: UnableToLegalize;
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default:
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return UnableToLegalize;
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}
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}
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void LegalizerHelper::extractParts(unsigned Reg, LLT Ty, int NumParts,
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SmallVectorImpl<unsigned> &VRegs) {
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for (int i = 0; i < NumParts; ++i)
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VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
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MIRBuilder.buildUnmerge(VRegs, Reg);
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}
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static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
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switch (Opcode) {
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case TargetOpcode::G_FREM:
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return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
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case TargetOpcode::G_FPOW:
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return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
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}
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llvm_unreachable("Unknown libcall function");
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::libcall(MachineInstr &MI) {
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LLT Ty = MRI.getType(MI.getOperand(0).getReg());
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unsigned Size = Ty.getSizeInBits();
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MIRBuilder.setInstr(MI);
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switch (MI.getOpcode()) {
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default:
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return UnableToLegalize;
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case TargetOpcode::G_FPOW:
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case TargetOpcode::G_FREM: {
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auto &Ctx = MIRBuilder.getMF().getFunction()->getContext();
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Type *Ty = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
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auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
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auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
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auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
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const char *Name = TLI.getLibcallName(Libcall);
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MIRBuilder.getMF().getFrameInfo().setHasCalls(true);
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CLI.lowerCall(
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MIRBuilder, TLI.getLibcallCallingConv(Libcall),
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MachineOperand::CreateES(Name), {MI.getOperand(0).getReg(), Ty},
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{{MI.getOperand(1).getReg(), Ty}, {MI.getOperand(2).getReg(), Ty}});
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MI.eraseFromParent();
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return Legalized;
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}
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}
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}
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LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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unsigned TypeIdx,
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LLT NarrowTy) {
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// FIXME: Don't know how to handle secondary types yet.
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if (TypeIdx != 0)
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return UnableToLegalize;
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MIRBuilder.setInstr(MI);
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switch (MI.getOpcode()) {
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default:
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return UnableToLegalize;
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case TargetOpcode::G_ADD: {
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// Expand in terms of carry-setting/consuming G_ADDE instructions.
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int NumParts = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() /
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NarrowTy.getSizeInBits();
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SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
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extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
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extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
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unsigned CarryIn = MRI.createGenericVirtualRegister(LLT::scalar(1));
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MIRBuilder.buildConstant(CarryIn, 0);
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for (int i = 0; i < NumParts; ++i) {
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unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
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unsigned CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
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MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
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Src2Regs[i], CarryIn);
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DstRegs.push_back(DstReg);
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CarryIn = CarryOut;
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}
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unsigned DstReg = MI.getOperand(0).getReg();
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MIRBuilder.buildMerge(DstReg, DstRegs);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_INSERT: {
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if (TypeIdx != 0)
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return UnableToLegalize;
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int64_t NarrowSize = NarrowTy.getSizeInBits();
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int NumParts =
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MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
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SmallVector<unsigned, 2> SrcRegs, DstRegs;
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SmallVector<uint64_t, 2> Indexes;
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extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
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unsigned OpReg = MI.getOperand(2).getReg();
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int64_t OpStart = MI.getOperand(3).getImm();
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int64_t OpSize = MRI.getType(OpReg).getSizeInBits();
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for (int i = 0; i < NumParts; ++i) {
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unsigned DstStart = i * NarrowSize;
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if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
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// No part of the insert affects this subregister, forward the original.
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DstRegs.push_back(SrcRegs[i]);
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continue;
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} else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
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// The entire subregister is defined by this insert, forward the new
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// value.
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DstRegs.push_back(OpReg);
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continue;
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}
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// OpSegStart is where this destination segment would start in OpReg if it
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// extended infinitely in both directions.
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int64_t ExtractOffset, InsertOffset, SegSize;
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if (OpStart < DstStart) {
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InsertOffset = 0;
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ExtractOffset = DstStart - OpStart;
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SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
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} else {
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InsertOffset = OpStart - DstStart;
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ExtractOffset = 0;
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SegSize =
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std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
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}
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unsigned SegReg = OpReg;
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if (ExtractOffset != 0 || SegSize != OpSize) {
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// A genuine extract is needed.
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SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
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MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
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}
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unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
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MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
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DstRegs.push_back(DstReg);
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}
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assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
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MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_LOAD: {
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unsigned NarrowSize = NarrowTy.getSizeInBits();
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int NumParts =
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MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
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LLT NarrowPtrTy = LLT::pointer(
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MRI.getType(MI.getOperand(1).getReg()).getAddressSpace(), NarrowSize);
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SmallVector<unsigned, 2> DstRegs;
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for (int i = 0; i < NumParts; ++i) {
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unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
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unsigned SrcReg = MRI.createGenericVirtualRegister(NarrowPtrTy);
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unsigned Offset = MRI.createGenericVirtualRegister(LLT::scalar(64));
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MIRBuilder.buildConstant(Offset, i * NarrowSize / 8);
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MIRBuilder.buildGEP(SrcReg, MI.getOperand(1).getReg(), Offset);
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// TODO: This is conservatively correct, but we probably want to split the
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// memory operands in the future.
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MIRBuilder.buildLoad(DstReg, SrcReg, **MI.memoperands_begin());
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DstRegs.push_back(DstReg);
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}
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unsigned DstReg = MI.getOperand(0).getReg();
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MIRBuilder.buildMerge(DstReg, DstRegs);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_STORE: {
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unsigned NarrowSize = NarrowTy.getSizeInBits();
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int NumParts =
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MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
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LLT NarrowPtrTy = LLT::pointer(
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MRI.getType(MI.getOperand(1).getReg()).getAddressSpace(), NarrowSize);
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SmallVector<unsigned, 2> SrcRegs;
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extractParts(MI.getOperand(0).getReg(), NarrowTy, NumParts, SrcRegs);
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for (int i = 0; i < NumParts; ++i) {
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unsigned DstReg = MRI.createGenericVirtualRegister(NarrowPtrTy);
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unsigned Offset = MRI.createGenericVirtualRegister(LLT::scalar(64));
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MIRBuilder.buildConstant(Offset, i * NarrowSize / 8);
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MIRBuilder.buildGEP(DstReg, MI.getOperand(1).getReg(), Offset);
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// TODO: This is conservatively correct, but we probably want to split the
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// memory operands in the future.
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MIRBuilder.buildStore(SrcRegs[i], DstReg, **MI.memoperands_begin());
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}
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_CONSTANT: {
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unsigned NarrowSize = NarrowTy.getSizeInBits();
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int NumParts =
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MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
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const APInt &Cst = MI.getOperand(1).getCImm()->getValue();
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LLVMContext &Ctx = MIRBuilder.getMF().getFunction()->getContext();
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SmallVector<unsigned, 2> DstRegs;
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for (int i = 0; i < NumParts; ++i) {
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unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
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ConstantInt *CI =
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ConstantInt::get(Ctx, Cst.lshr(NarrowSize * i).trunc(NarrowSize));
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MIRBuilder.buildConstant(DstReg, *CI);
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DstRegs.push_back(DstReg);
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}
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unsigned DstReg = MI.getOperand(0).getReg();
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MIRBuilder.buildMerge(DstReg, DstRegs);
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MI.eraseFromParent();
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return Legalized;
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}
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}
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
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MIRBuilder.setInstr(MI);
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switch (MI.getOpcode()) {
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default:
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return UnableToLegalize;
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case TargetOpcode::G_ADD:
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case TargetOpcode::G_AND:
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case TargetOpcode::G_MUL:
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case TargetOpcode::G_OR:
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case TargetOpcode::G_XOR:
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case TargetOpcode::G_SUB:
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case TargetOpcode::G_SHL: {
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// Perform operation at larger width (any extension is fine here, high bits
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// don't affect the result) and then truncate the result back to the
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// original type.
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unsigned Src1Ext = MRI.createGenericVirtualRegister(WideTy);
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unsigned Src2Ext = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildAnyExt(Src1Ext, MI.getOperand(1).getReg());
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MIRBuilder.buildAnyExt(Src2Ext, MI.getOperand(2).getReg());
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unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildInstr(MI.getOpcode())
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.addDef(DstExt)
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.addUse(Src1Ext)
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.addUse(Src2Ext);
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MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_SDIV:
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case TargetOpcode::G_UDIV:
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case TargetOpcode::G_ASHR:
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case TargetOpcode::G_LSHR: {
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unsigned ExtOp = MI.getOpcode() == TargetOpcode::G_SDIV ||
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MI.getOpcode() == TargetOpcode::G_ASHR
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? TargetOpcode::G_SEXT
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: TargetOpcode::G_ZEXT;
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unsigned LHSExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildInstr(ExtOp).addDef(LHSExt).addUse(
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MI.getOperand(1).getReg());
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unsigned RHSExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildInstr(ExtOp).addDef(RHSExt).addUse(
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MI.getOperand(2).getReg());
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unsigned ResExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildInstr(MI.getOpcode())
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.addDef(ResExt)
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.addUse(LHSExt)
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.addUse(RHSExt);
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MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), ResExt);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_SELECT: {
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if (TypeIdx != 0)
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return UnableToLegalize;
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// Perform operation at larger width (any extension is fine here, high bits
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// don't affect the result) and then truncate the result back to the
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// original type.
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unsigned Src1Ext = MRI.createGenericVirtualRegister(WideTy);
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unsigned Src2Ext = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildAnyExt(Src1Ext, MI.getOperand(2).getReg());
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MIRBuilder.buildAnyExt(Src2Ext, MI.getOperand(3).getReg());
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unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildInstr(TargetOpcode::G_SELECT)
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.addDef(DstExt)
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.addReg(MI.getOperand(1).getReg())
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.addUse(Src1Ext)
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.addUse(Src2Ext);
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MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_FPTOSI:
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case TargetOpcode::G_FPTOUI: {
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if (TypeIdx != 0)
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return UnableToLegalize;
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unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildInstr(MI.getOpcode())
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.addDef(DstExt)
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.addUse(MI.getOperand(1).getReg());
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MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_SITOFP:
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case TargetOpcode::G_UITOFP: {
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if (TypeIdx != 1)
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return UnableToLegalize;
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unsigned Src = MI.getOperand(1).getReg();
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unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
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if (MI.getOpcode() == TargetOpcode::G_SITOFP) {
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MIRBuilder.buildSExt(SrcExt, Src);
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} else {
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assert(MI.getOpcode() == TargetOpcode::G_UITOFP && "Unexpected conv op");
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MIRBuilder.buildZExt(SrcExt, Src);
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}
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MIRBuilder.buildInstr(MI.getOpcode())
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.addDef(MI.getOperand(0).getReg())
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.addUse(SrcExt);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_INSERT: {
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if (TypeIdx != 0)
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return UnableToLegalize;
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unsigned Src = MI.getOperand(1).getReg();
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unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildAnyExt(SrcExt, Src);
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unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
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auto MIB = MIRBuilder.buildInsert(DstExt, SrcExt, MI.getOperand(2).getReg(),
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MI.getOperand(3).getImm());
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for (unsigned OpNum = 4; OpNum < MI.getNumOperands(); OpNum += 2) {
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MIB.addReg(MI.getOperand(OpNum).getReg());
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MIB.addImm(MI.getOperand(OpNum + 1).getImm());
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}
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MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_LOAD: {
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assert(alignTo(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(), 8) ==
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WideTy.getSizeInBits() &&
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"illegal to increase number of bytes loaded");
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unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildLoad(DstExt, MI.getOperand(1).getReg(),
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**MI.memoperands_begin());
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MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_STORE: {
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if (MRI.getType(MI.getOperand(0).getReg()) != LLT::scalar(1) ||
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WideTy != LLT::scalar(8))
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return UnableToLegalize;
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auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
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auto Content = TLI.getBooleanContents(false, false);
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unsigned ExtOp = TargetOpcode::G_ANYEXT;
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if (Content == TargetLoweringBase::ZeroOrOneBooleanContent)
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ExtOp = TargetOpcode::G_ZEXT;
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else if (Content == TargetLoweringBase::ZeroOrNegativeOneBooleanContent)
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ExtOp = TargetOpcode::G_SEXT;
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else
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ExtOp = TargetOpcode::G_ANYEXT;
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unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildInstr(ExtOp).addDef(SrcExt).addUse(
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MI.getOperand(0).getReg());
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MIRBuilder.buildStore(SrcExt, MI.getOperand(1).getReg(),
|
|
**MI.memoperands_begin());
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_CONSTANT: {
|
|
unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
|
|
MIRBuilder.buildConstant(DstExt, *MI.getOperand(1).getCImm());
|
|
MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_FCONSTANT: {
|
|
unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
|
|
MIRBuilder.buildFConstant(DstExt, *MI.getOperand(1).getFPImm());
|
|
MIRBuilder.buildFPTrunc(MI.getOperand(0).getReg(), DstExt);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_BRCOND: {
|
|
unsigned TstExt = MRI.createGenericVirtualRegister(WideTy);
|
|
MIRBuilder.buildAnyExt(TstExt, MI.getOperand(0).getReg());
|
|
MIRBuilder.buildBrCond(TstExt, *MI.getOperand(1).getMBB());
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_ICMP: {
|
|
assert(TypeIdx == 1 && "unable to legalize predicate");
|
|
bool IsSigned = CmpInst::isSigned(
|
|
static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()));
|
|
unsigned Op0Ext = MRI.createGenericVirtualRegister(WideTy);
|
|
unsigned Op1Ext = MRI.createGenericVirtualRegister(WideTy);
|
|
if (IsSigned) {
|
|
MIRBuilder.buildSExt(Op0Ext, MI.getOperand(2).getReg());
|
|
MIRBuilder.buildSExt(Op1Ext, MI.getOperand(3).getReg());
|
|
} else {
|
|
MIRBuilder.buildZExt(Op0Ext, MI.getOperand(2).getReg());
|
|
MIRBuilder.buildZExt(Op1Ext, MI.getOperand(3).getReg());
|
|
}
|
|
MIRBuilder.buildICmp(
|
|
static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()),
|
|
MI.getOperand(0).getReg(), Op0Ext, Op1Ext);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_GEP: {
|
|
assert(TypeIdx == 1 && "unable to legalize pointer of GEP");
|
|
unsigned OffsetExt = MRI.createGenericVirtualRegister(WideTy);
|
|
MIRBuilder.buildSExt(OffsetExt, MI.getOperand(2).getReg());
|
|
MI.getOperand(2).setReg(OffsetExt);
|
|
return Legalized;
|
|
}
|
|
}
|
|
}
|
|
|
|
LegalizerHelper::LegalizeResult
|
|
LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
|
|
using namespace TargetOpcode;
|
|
MIRBuilder.setInstr(MI);
|
|
|
|
switch(MI.getOpcode()) {
|
|
default:
|
|
return UnableToLegalize;
|
|
case TargetOpcode::G_SREM:
|
|
case TargetOpcode::G_UREM: {
|
|
unsigned QuotReg = MRI.createGenericVirtualRegister(Ty);
|
|
MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
|
|
.addDef(QuotReg)
|
|
.addUse(MI.getOperand(1).getReg())
|
|
.addUse(MI.getOperand(2).getReg());
|
|
|
|
unsigned ProdReg = MRI.createGenericVirtualRegister(Ty);
|
|
MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
|
|
MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
|
|
ProdReg);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_SMULO:
|
|
case TargetOpcode::G_UMULO: {
|
|
// Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
|
|
// result.
|
|
unsigned Res = MI.getOperand(0).getReg();
|
|
unsigned Overflow = MI.getOperand(1).getReg();
|
|
unsigned LHS = MI.getOperand(2).getReg();
|
|
unsigned RHS = MI.getOperand(3).getReg();
|
|
|
|
MIRBuilder.buildMul(Res, LHS, RHS);
|
|
|
|
unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
|
|
? TargetOpcode::G_SMULH
|
|
: TargetOpcode::G_UMULH;
|
|
|
|
unsigned HiPart = MRI.createGenericVirtualRegister(Ty);
|
|
MIRBuilder.buildInstr(Opcode)
|
|
.addDef(HiPart)
|
|
.addUse(LHS)
|
|
.addUse(RHS);
|
|
|
|
unsigned Zero = MRI.createGenericVirtualRegister(Ty);
|
|
MIRBuilder.buildConstant(Zero, 0);
|
|
MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_FNEG: {
|
|
// TODO: Handle vector types once we are able to
|
|
// represent them.
|
|
if (Ty.isVector())
|
|
return UnableToLegalize;
|
|
unsigned Res = MI.getOperand(0).getReg();
|
|
Type *ZeroTy;
|
|
LLVMContext &Ctx = MIRBuilder.getMF().getFunction()->getContext();
|
|
switch (Ty.getSizeInBits()) {
|
|
case 16:
|
|
ZeroTy = Type::getHalfTy(Ctx);
|
|
break;
|
|
case 32:
|
|
ZeroTy = Type::getFloatTy(Ctx);
|
|
break;
|
|
case 64:
|
|
ZeroTy = Type::getDoubleTy(Ctx);
|
|
break;
|
|
default:
|
|
llvm_unreachable("unexpected floating-point type");
|
|
}
|
|
ConstantFP &ZeroForNegation =
|
|
*cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
|
|
unsigned Zero = MRI.createGenericVirtualRegister(Ty);
|
|
MIRBuilder.buildFConstant(Zero, ZeroForNegation);
|
|
MIRBuilder.buildInstr(TargetOpcode::G_FSUB)
|
|
.addDef(Res)
|
|
.addUse(Zero)
|
|
.addUse(MI.getOperand(1).getReg());
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
case TargetOpcode::G_FSUB: {
|
|
// Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
|
|
// First, check if G_FNEG is marked as Lower. If so, we may
|
|
// end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
|
|
if (LI.getAction({G_FNEG, Ty}).first == LegalizerInfo::Lower)
|
|
return UnableToLegalize;
|
|
unsigned Res = MI.getOperand(0).getReg();
|
|
unsigned LHS = MI.getOperand(1).getReg();
|
|
unsigned RHS = MI.getOperand(2).getReg();
|
|
unsigned Neg = MRI.createGenericVirtualRegister(Ty);
|
|
MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
|
|
MIRBuilder.buildInstr(TargetOpcode::G_FADD)
|
|
.addDef(Res)
|
|
.addUse(LHS)
|
|
.addUse(Neg);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
}
|
|
}
|
|
|
|
LegalizerHelper::LegalizeResult
|
|
LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
|
|
LLT NarrowTy) {
|
|
// FIXME: Don't know how to handle secondary types yet.
|
|
if (TypeIdx != 0)
|
|
return UnableToLegalize;
|
|
switch (MI.getOpcode()) {
|
|
default:
|
|
return UnableToLegalize;
|
|
case TargetOpcode::G_ADD: {
|
|
unsigned NarrowSize = NarrowTy.getSizeInBits();
|
|
unsigned DstReg = MI.getOperand(0).getReg();
|
|
int NumParts = MRI.getType(DstReg).getSizeInBits() / NarrowSize;
|
|
|
|
MIRBuilder.setInstr(MI);
|
|
|
|
SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
|
|
extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
|
|
extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
|
|
|
|
for (int i = 0; i < NumParts; ++i) {
|
|
unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
|
|
MIRBuilder.buildAdd(DstReg, Src1Regs[i], Src2Regs[i]);
|
|
DstRegs.push_back(DstReg);
|
|
}
|
|
|
|
MIRBuilder.buildMerge(DstReg, DstRegs);
|
|
MI.eraseFromParent();
|
|
return Legalized;
|
|
}
|
|
}
|
|
}
|