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clang-p2996/llvm/test/CodeGen/Hexagon
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Krzysztof Parzyszek 2182b4b7b3 [Hexagon] Use -mattr to select HVX mode in a testcase, NFC 
llvm-svn: 299582
2017-04-05 19:46:37 +00:00
..
intrinsics
[Hexagon] Add intrinsics for masked vector stores
2017-02-22 21:23:09 +00:00
loop-idiom
[Hexagon] Avoid infinite loops in HexagonLoopIdiomRecognition
2017-03-23 23:01:22 +00:00
vect
[Hexagon] Generate extract instructions more aggressively
2017-02-28 23:27:33 +00:00
absaddr-store.ll
…
absimm.ll
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adde.ll
[Hexagon] Propagate zext of i1 into arithmetic code in selection DAG
2017-03-09 16:29:30 +00:00
addh-sext-trunc.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
addh-shifted.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
addh.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
addr-calc-opt.ll
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addrmode-indoff.ll
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alu64.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
always-ext.ll
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anti-dep-partial.mir
Move .mir tests to appropriate directories
2016-12-09 19:08:15 +00:00
args.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
ashift-left-right.ll
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Atomics.ll
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avoid-predspill-calleesaved.ll
[Hexagon] Start using regmasks on calls
2017-02-17 22:14:51 +00:00
avoid-predspill.ll
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barrier-flag.ll
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base-offset-addr.ll
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base-offset-post.ll
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bit-bitsplit-at.ll
[Hexagon] Fixes to the bitsplit generation
2017-03-09 22:02:14 +00:00
bit-bitsplit-src.ll
[Hexagon] Generate bitsplit instruction
2017-03-07 23:08:35 +00:00
bit-bitsplit.ll
[Hexagon] Generate bitsplit instruction
2017-03-07 23:08:35 +00:00
bit-eval.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
bit-ext-sat.ll
[Hexagon] Handle saturations in Hexagon bit tracker
2017-02-23 22:11:52 +00:00
bit-extract-off.ll
[Hexagon] Use correct offset when extracting from the high word
2017-03-08 15:46:28 +00:00
bit-extract.ll
[Hexagon] Generate extract instructions more aggressively
2017-02-28 23:27:33 +00:00
bit-extractu-half.ll
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bit-gen-rseq.ll
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bit-has.ll
[Hexagon] Check for presence before looking registers up in bit tracker
2017-03-07 23:12:04 +00:00
bit-loop-rc-mismatch.ll
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bit-loop.ll
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bit-phi.ll
[Hexagon] Do not insert instructions before PHI nodes
2017-03-07 14:20:19 +00:00
bit-rie.ll
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bit-skip-byval.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
bit-validate-reg.ll
[Hexagon] Generate extract instructions more aggressively
2017-02-28 23:27:33 +00:00
bit-visit-flowq.ll
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bitconvert-vector.ll
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bitmanip.ll
[Hexagon] Patterns for CTPOP, BSWAP and BITREVERSE
2017-02-23 15:02:09 +00:00
block-addr.ll
[Hexagon] Early-if-convert branches that may exit the loop
2017-03-06 17:24:04 +00:00
block-ranges-nodef.ll
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branch-non-mbb.ll
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branchfolder-keep-impdef.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
BranchPredict.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
brev_ld.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
brev_st.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
bugAsmHWloop.ll
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build-vector-shuffle.ll
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builtin-expect.ll
[Hexagon] Pick the right branch opcode depending on branch probabilities
2017-03-02 21:49:49 +00:00
builtin-prefetch-offset.ll
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builtin-prefetch.ll
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calling-conv-2.ll
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callr-dep-edge.ll
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cext-check.ll
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cext-valid-packet1.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
cext-valid-packet2.ll
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cext.ll
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cexti16.ll
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cfi-late.ll
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cfi-offset.ll
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checktabs.ll
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circ_ld.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
circ_ldd_bug.ll
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circ_ldw.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
circ_st.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
circ-load-isel.ll
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clr_set_toggle.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
cmp_pred2.ll
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cmp_pred_reg.ll
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cmp_pred.ll
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cmp-extend.ll
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cmp-promote.ll
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cmp-to-genreg.ll
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cmp-to-predreg.ll
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cmp.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
cmpb_pred.ll
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cmpb-eq.ll
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combine_ir.ll
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combine.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
common-gep-basic.ll
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common-gep-icm.ll
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compound.ll
[Hexagon] Start using regmasks on calls
2017-02-17 22:14:51 +00:00
const64.ll
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const-pool-tf.ll
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constp-clb.ll
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constp-combine-neg.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
constp-ctb.ll
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constp-extract.ll
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constp-physreg.ll
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constp-rewrite-branches.ll
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constp-rseq.ll
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constp-vsplat.ll
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convert-to-dot-old.ll
[Hexagon] Pick a dot-old instruction that matches the architecture
2017-03-06 17:03:16 +00:00
convertdptoint.ll
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convertdptoll.ll
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convertsptoint.ll
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convertsptoll.ll
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copy-to-combine-dbg.ll
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csr-func-usedef.ll
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ctor.ll
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dadd.ll
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dead-store-stack.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
dmul.ll
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double.ll
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doubleconvert-ieee-rnd-near.ll
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dsub.ll
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dualstore.ll
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duplex.ll
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early-if-conversion-bug1.ll
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early-if-merge-loop.ll
[Hexagon] Early-if-convert branches that may exit the loop
2017-03-06 17:24:04 +00:00
early-if-phi-i1.ll
[Hexagon] Add -march=hexagon to a testcase
2017-03-21 16:59:40 +00:00
early-if-spare.ll
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early-if-vecpi.ll
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early-if-vecpred.ll
[Hexagon] Skip blocks that define vector predicate registers in early-if
2017-03-02 18:10:59 +00:00
early-if.ll
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eh_return.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
eliminate-pred-spill.ll
[Hexagon] Use -mattr to select HVX mode in a testcase, NFC
2017-04-05 19:46:37 +00:00
expand-condsets-basic.ll
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expand-condsets-dead-bad.ll
[Hexagon] Mark dead defs as <dead> in expand-condsets
2017-03-06 17:09:06 +00:00
expand-condsets-dead-pred.ll
[Hexagon] Mark dead defs as <dead> in expand-condsets
2017-03-06 17:09:06 +00:00
expand-condsets-def-undef.mir
[Hexagon] Separate Hexagon subreg indices for different register classes
2016-11-09 16:19:08 +00:00
expand-condsets-extend.ll
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expand-condsets-impuse.mir
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expand-condsets-pred-undef.ll
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expand-condsets-rm-reg.mir
Bring back 2>&1 redirection for this test
2017-02-22 19:16:33 +00:00
expand-condsets-rm-segment.ll
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expand-condsets-same-inputs.mir
[Hexagon] Don't expand mux instructions with both sources identical
2016-10-31 15:45:09 +00:00
expand-condsets-undef2.ll
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expand-condsets-undef.ll
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expand-vstorerw-undef2.ll
[Hexagon] Remove dead defs from the live set when expanding wstores
2017-01-18 23:11:40 +00:00
expand-vstorerw-undef.ll
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extload-combine.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
extract-basic.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
fadd.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
fcmp.ll
…
find-loop-instr.ll
[Hexagon] Fix insertBranch for loops with multiple ENDLOOP instructions
2017-02-02 19:36:37 +00:00
fixed-spill-mutable.ll
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float-amode.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
float.ll
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floatconvert-ieee-rnd-near.ll
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fminmax.ll
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fmul.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
frame-offset-overflow.ll
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frame.ll
…
fsel.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
fsub.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
fusedandshift.ll
[Hexagon] Generate extract instructions more aggressively
2017-02-28 23:27:33 +00:00
gp-plus-offset-load.ll
…
gp-plus-offset-store.ll
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gp-rel.ll
[Hexagon] Adding gp+ to the syntax of gp-relative instructions
2017-02-06 23:18:57 +00:00
hwloop1.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
hwloop2.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
hwloop3.ll
…
hwloop4.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
hwloop5.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
hwloop-cleanup.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
hwloop-const.ll
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hwloop-crit-edge.ll
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hwloop-dbg.ll
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hwloop-le.ll
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hwloop-loop1.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
hwloop-lt1.ll
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hwloop-lt.ll
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hwloop-missed.ll
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hwloop-ne.ll
…
hwloop-noreturn-call.ll
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hwloop-ph-deadcode.ll
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hwloop-pos-ivbump1.ll
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hwloop-preh.ll
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hwloop-preheader.ll
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hwloop-range.ll
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hwloop-recursion.ll
…
hwloop-wrap2.ll
…
hwloop-wrap.ll
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i1_VarArg.ll
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i8_VarArg.ll
…
i16_VarArg.ll
…
idxload-with-zero-offset.ll
…
ifcvt-diamond-bad.ll
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ifcvt-diamond-bug-2016-08-26.ll
[Hexagon] Fix typo in HexagonEarlyIfCConv.cpp
2017-03-31 20:36:00 +00:00
ifcvt-edge-weight.ll
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ifcvt-impuse-livein.mir
…
ifcvt-live-subreg.mir
…
ifcvt-simple-bprob.ll
[IfConversion] Only renormalize probabilities if branches are analyzable
2017-03-06 19:12:42 +00:00
indirect-br.ll
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inline-asm-hexagon.ll
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inline-asm-i1.ll
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inline-asm-qv.ll
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inline-asm-vecpred128.ll
[Hexagon] Properly handle 'q' constraint in 128-byte vector mode
2017-03-02 17:50:24 +00:00
insert4.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
insert-basic.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
is-legal-void.ll
…
isel-exti1.ll
[Hexagon] Fix instruction selection for sign-extending i1 to i64
2017-02-28 22:37:01 +00:00
isel-i1arg-crash.ll
[Hexagon] Fix lowering of formal arguments of type i1
2017-03-01 17:30:10 +00:00
isel-op-zext-i1.ll
[Hexagon] Propagate zext of i1 into arithmetic code in selection DAG
2017-03-09 16:29:30 +00:00
lit.local.cfg
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livephysregs-lane-masks2.mir
…
livephysregs-lane-masks.mir
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loadi1-G0.ll
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loadi1-v4-G0.ll
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loadi1-v4.ll
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loadi1.ll
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long-calls.ll
…
loop-prefetch.ll
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lower-extract-subvector.ll
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macint.ll
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maxd.ll
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maxh.ll
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maxud.ll
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maxuw.ll
…
maxw.ll
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mem-fi-add.ll
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memcpy-likely-aligned.ll
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memops1.ll
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memops2.ll
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memops3.ll
…
memops-stack.ll
…
memops.ll
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mind.ll
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minu-zext-8.ll
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minu-zext-16.ll
…
minud.ll
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minuw.ll
…
minw.ll
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misaligned_double_vector_store_not_fast.ll
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misaligned-access.ll
…
misched-top-rptracker-sync.ll
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mpy.ll
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mulhs.ll
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mux-basic.ll
…
newvaluejump2.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
newvaluejump3.ll
[Hexagon] Avoid IMPLICIT_DEFs as new-value producers
2017-02-23 17:47:34 +00:00
newvaluejump.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
newvalueSameReg.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
newvaluestore.ll
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NVJumpCmp.ll
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opt-addr-mode.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
opt-fabs.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
opt-fneg.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
opt-spill-volatile.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
packetize_cond_inst.ll
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packetize-cfi-location.ll
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packetize-return-arg.ll
…
packetize-tailcall-arg.ll
…
peephole-kill-flags.ll
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peephole-op-swap.ll
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pic-jumptables.ll
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pic-local.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
pic-regusage.ll
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pic-simple.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
pic-static.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
post-inc-aa-metadata.ll
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post-ra-kill-update.mir
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postinc-load.ll
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postinc-offset.ll
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postinc-store.ll
…
pred-absolute-store.ll
[RDF] Remove the map of reaching defs from copy propagation
2017-03-10 22:44:24 +00:00
pred-gp.ll
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pred-instrs.ll
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predicate-copy.ll
…
predicate-logical.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
predicate-rcmp.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
propagate-vcombine.ll
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rdf-copy-undef2.ll
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rdf-copy.ll
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rdf-dead-loop.ll
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rdf-extra-livein.ll
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rdf-filter-defs.ll
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rdf-ignore-undef.ll
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rdf-inline-asm-fixed.ll
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rdf-inline-asm.ll
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rdf-multiple-phis-up.ll
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rdf-phi-shadows.ll
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rdf-phi-up.ll
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rdf-reset-kills.ll
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readcyclecounter.ll
[Hexagon] Implement @llvm.readcyclecounter()
2017-02-22 22:28:47 +00:00
reg-scavengebug-3.ll
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reg-scavenger-valid-slot.ll
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regalloc-bad-undef.mir
[Hexagon] Separate Hexagon subreg indices for different register classes
2016-11-09 16:19:08 +00:00
regalloc-block-overlap.ll
Treat segment [B, E) as not overlapping block with boundaries [A, B)
2017-01-18 23:12:19 +00:00
relax.ll
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remove_lsr.ll
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remove-endloop.ll
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restore-single-reg.ll
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ret-struct-by-val.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
runtime-stkchk.ll
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sdata-array.ll
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sdata-basic.ll
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sdr-basic.ll
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sdr-shr32.ll
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section_7275.ll
[Hexagon] Adding gp+ to the syntax of gp-relative instructions
2017-02-06 23:18:57 +00:00
select-instr-align.ll
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sf-min-max.ll
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sffms.ll
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shrink-frame-basic.ll
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signed_immediates.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
simple_addend.ll
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simpletailcall.ll
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split-const32-const64.ll
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stack-align1.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
stack-align2.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
stack-alloca1.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
stack-alloca2.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
static.ll
[Hexagon] Adding gp+ to the syntax of gp-relative instructions
2017-02-06 23:18:57 +00:00
store-shift.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
store-widen-aliased-load.ll
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store-widen-negv2.ll
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store-widen-negv.ll
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store-widen.ll
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storerd-io-over-rr.ll
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storerinewabs.ll
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struct_args_large.ll
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struct_args.ll
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sube.ll
[Hexagon] Propagate zext of i1 into arithmetic code in selection DAG
2017-03-09 16:29:30 +00:00
subi-asl.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
SUnit-boundary-prob.ll
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swp-const-tc.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
swp-dag-phi.ll
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swp-epilog-phi10.ll
Fix two bugs in the pipeliner in renaming phis in the prolog and epilog
2016-12-22 18:49:55 +00:00
swp-epilog-reuse-1.ll
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swp-epilog-reuse.ll
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swp-matmul-bitext.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
swp-max.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
swp-multi-loops.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
swp-prolog-phi4.ll
Fix two bugs in the pipeliner in renaming phis in the prolog and epilog
2016-12-22 18:49:55 +00:00
swp-stages4.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
swp-stages5.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
swp-vect-dotprod.ll
…
swp-vmult.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
swp-vsum.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
tail-call-mem-intrinsics.ll
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tail-call-trunc.ll
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tail-dup-subreg-abort.ll
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tail-dup-subreg-map.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
tailcall_fastcc_ccc.ll
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tfr-to-combine.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
tls_pic.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
tls_static.ll
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two-crash.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
undo-dag-shift.ll
[Hexagon] Undo shift folding where it could simplify addressing mode
2017-02-24 23:34:24 +00:00
union-1.ll
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usr-ovf-dep.ll
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v6vec-vprint.ll
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v60-cur.ll
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v60-vsel1.ll
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v60Intrins.ll
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v60small.ll
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v60Vasr.ll
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vaddh.ll
[Hexagon] Replace instruction definitions with auto-generated ones
2017-02-10 15:33:13 +00:00
validate-offset.ll
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vassign-to-combine.ll
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vdmpy-halide-test.ll
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vec-pred-spill1.ll
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vector-align.ll
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vector-ext-load.ll
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vload-postinc-sel.ll
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vmpa-halide-test.ll
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vpack_eo.ll
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vselect-pseudo.ll
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vsplat-isel.ll
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zextloadi1.ll
…