0ba63b2f22
Add additional tests showing missed opportunities when using loop guards for reasoning in SCEV, depending on the order the guards appear in the IR.
65 lines
2.9 KiB
LLVM
65 lines
2.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -p indvars -S %s | FileCheck %s
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target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
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target triple = "arm64-apple-macosx15.0.0"
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define i32 @guards_applied_to_add_rec(ptr %dst) {
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; CHECK-LABEL: define i32 @guards_applied_to_add_rec(
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; CHECK-SAME: ptr [[DST:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[OUTER_HEADER:.*]]
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; CHECK: [[OUTER_HEADER]]:
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; CHECK-NEXT: [[OUTER_IV_0:%.*]] = phi i32 [ 2, %[[ENTRY]] ], [ [[OUTER_IV_0_NEXT:%.*]], %[[OUTER_LATCH:.*]] ]
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; CHECK-NEXT: [[OUTER_IV_1:%.*]] = phi i32 [ 1, %[[ENTRY]] ], [ [[OUTER_IV_0]], %[[OUTER_LATCH]] ]
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; CHECK-NEXT: [[SHR28:%.*]] = lshr i32 [[OUTER_IV_1]], 1
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; CHECK-NEXT: [[PRE:%.*]] = icmp samesign ult i32 [[OUTER_IV_1]], 2
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; CHECK-NEXT: br i1 [[PRE]], label %[[OUTER_LATCH]], label %[[INNER_PREHEADER:.*]]
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; CHECK: [[INNER_PREHEADER]]:
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; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[SHR28]] to i64
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; CHECK-NEXT: br label %[[INNER:.*]]
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; CHECK: [[INNER]]:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[INNER_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[INNER]] ]
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; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr i32, ptr [[DST]], i64 [[INDVARS_IV]]
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; CHECK-NEXT: [[TMP1:%.*]] = trunc nuw nsw i64 [[INDVARS_IV]] to i32
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; CHECK-NEXT: store i32 [[TMP1]], ptr [[GEP_DST]], align 4
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[CMP29:%.*]] = icmp samesign ult i64 [[INDVARS_IV_NEXT]], [[TMP0]]
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; CHECK-NEXT: br i1 [[CMP29]], label %[[INNER]], label %[[OUTER_LATCH_LOOPEXIT:.*]]
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; CHECK: [[OUTER_LATCH_LOOPEXIT]]:
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; CHECK-NEXT: br label %[[OUTER_LATCH]]
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; CHECK: [[OUTER_LATCH]]:
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; CHECK-NEXT: [[OUTER_IV_0_NEXT]] = add nuw i32 [[OUTER_IV_0]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[OUTER_IV_0_NEXT]], -2147483647
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; CHECK-NEXT: br i1 [[EXITCOND]], label %[[OUTER_HEADER]], label %[[EXIT:.*]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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br label %outer.header
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outer.header:
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%outer.iv.0 = phi i32 [ 2, %entry ], [ %outer.iv.0.next, %outer.latch ]
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%outer.iv.1 = phi i32 [ 1, %entry ], [ %outer.iv.0, %outer.latch ]
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%shr28 = lshr i32 %outer.iv.1, 1
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%pre = icmp samesign ult i32 %outer.iv.1, 2
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br i1 %pre, label %outer.latch, label %inner
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inner:
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%inner.iv = phi i32 [ 0, %outer.header ], [ %inc, %inner ]
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%ext.iv = zext nneg i32 %inner.iv to i64
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%gep.dst = getelementptr i32, ptr %dst, i64 %ext.iv
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store i32 %inner.iv, ptr %gep.dst, align 4
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%inc = add nuw nsw i32 %inner.iv, 1
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%cmp29 = icmp samesign ult i32 %inc, %shr28
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br i1 %cmp29, label %inner, label %outer.latch
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outer.latch:
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%outer.iv.0.next = add i32 %outer.iv.0, 1
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%outer.ec = icmp sgt i32 %outer.iv.0, 0
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br i1 %outer.ec, label %outer.header, label %exit
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exit:
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ret i32 0
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}
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