0ba63b2f22
Add additional tests showing missed opportunities when using loop guards for reasoning in SCEV, depending on the order the guards appear in the IR.
99 lines
3.7 KiB
LLVM
99 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -p indvars -S %s | FileCheck %s
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declare void @foo()
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define void @narrow_iv_precondition_order_1(ptr %start, i32 %base, i8 %n) {
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; CHECK-LABEL: define void @narrow_iv_precondition_order_1(
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; CHECK-SAME: ptr [[START:%.*]], i32 [[BASE:%.*]], i8 [[N:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[PRE_0:%.*]] = icmp sgt i32 [[BASE]], 0
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; CHECK-NEXT: br i1 [[PRE_0]], label %[[EXIT:.*]], label %[[PH:.*]]
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; CHECK: [[PH]]:
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; CHECK-NEXT: [[N_EXT:%.*]] = zext i8 [[N]] to i32
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; CHECK-NEXT: [[PRE_1:%.*]] = icmp sgt i32 [[BASE]], [[N_EXT]]
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; CHECK-NEXT: br i1 [[PRE_1]], label %[[LOOP_PREHEADER:.*]], label %[[EXIT]]
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; CHECK: [[LOOP_PREHEADER]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi ptr [ [[GEP:%.*]], %[[LOOP]] ], [ [[START]], %[[LOOP_PREHEADER]] ]
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; CHECK-NEXT: call void @foo()
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; CHECK-NEXT: [[END:%.*]] = load i8, ptr [[IV]], align 1
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; CHECK-NEXT: [[END_EXT:%.*]] = zext i8 [[END]] to i32
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; CHECK-NEXT: [[GEP]] = getelementptr inbounds i8, ptr [[IV]], i64 1
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; CHECK-NEXT: [[EC:%.*]] = icmp sgt i32 [[BASE]], [[END_EXT]]
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; CHECK-NEXT: br i1 [[EC]], label %[[LOOP]], label %[[EXIT_LOOPEXIT:.*]]
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; CHECK: [[EXIT_LOOPEXIT]]:
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; CHECK-NEXT: br label %[[EXIT]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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%pre.0 = icmp sgt i32 %base, 0
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br i1 %pre.0, label %exit, label %ph
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ph: ; preds = %entry
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%n.ext = zext i8 %n to i32
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%pre.1 = icmp sgt i32 %base, %n.ext
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br i1 %pre.1, label %loop, label %exit
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loop:
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%iv = phi ptr [ %start, %ph ], [ %gep, %loop ]
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call void @foo()
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%end = load i8, ptr %iv, align 1
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%end.ext = zext i8 %end to i32
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%gep = getelementptr inbounds i8, ptr %iv, i64 1
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%ec = icmp sgt i32 %base, %end.ext
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br i1 %ec, label %loop, label %exit
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exit:
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ret void
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}
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define void @narrow_iv_precondition_order_2(ptr %start, i32 %base, i8 %n) {
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; CHECK-LABEL: define void @narrow_iv_precondition_order_2(
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; CHECK-SAME: ptr [[START:%.*]], i32 [[BASE:%.*]], i8 [[N:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[N_EXT:%.*]] = zext i8 [[N]] to i32
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; CHECK-NEXT: [[PRE_1:%.*]] = icmp sgt i32 [[BASE]], [[N_EXT]]
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; CHECK-NEXT: br i1 [[PRE_1]], label %[[EXIT:.*]], label %[[PH:.*]]
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; CHECK: [[PH]]:
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; CHECK-NEXT: [[PRE_0:%.*]] = icmp sgt i32 [[BASE]], 0
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; CHECK-NEXT: br i1 [[PRE_0]], label %[[LOOP_PREHEADER:.*]], label %[[EXIT]]
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; CHECK: [[LOOP_PREHEADER]]:
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; CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[BASE]] to i8
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi ptr [ [[GEP:%.*]], %[[LOOP]] ], [ [[START]], %[[LOOP_PREHEADER]] ]
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; CHECK-NEXT: call void @foo()
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; CHECK-NEXT: [[END:%.*]] = load i8, ptr [[IV]], align 1
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; CHECK-NEXT: [[GEP]] = getelementptr inbounds i8, ptr [[IV]], i64 1
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; CHECK-NEXT: [[EC:%.*]] = icmp ugt i8 [[TMP0]], [[END]]
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; CHECK-NEXT: br i1 [[EC]], label %[[LOOP]], label %[[EXIT_LOOPEXIT:.*]]
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; CHECK: [[EXIT_LOOPEXIT]]:
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; CHECK-NEXT: br label %[[EXIT]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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%n.ext = zext i8 %n to i32
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%pre.1 = icmp sgt i32 %base, %n.ext
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br i1 %pre.1, label %exit, label %ph
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ph: ; preds = %entry
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%pre.0 = icmp sgt i32 %base, 0
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br i1 %pre.0, label %loop, label %exit
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loop:
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%iv = phi ptr [ %start, %ph ], [ %gep, %loop ]
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call void @foo()
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%end = load i8, ptr %iv, align 1
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%end.ext = zext i8 %end to i32
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%gep = getelementptr inbounds i8, ptr %iv, i64 1
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%ec = icmp sgt i32 %base, %end.ext
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br i1 %ec, label %loop, label %exit
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exit:
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ret void
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}
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