dcb834843e
This is only used by CodeGen. Moving it out of AMDGPUBaseInfo simplifies future changes to make some of it depend on the subtarget. Differential Revision: https://reviews.llvm.org/D144650
493 lines
18 KiB
C++
493 lines
18 KiB
C++
//=== lib/CodeGen/GlobalISel/AMDGPURegBankCombiner.cpp ---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass does combining of machine instructions at the generic MI level,
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// after register banks are known.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPULegalizerInfo.h"
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#include "AMDGPURegisterBankInfo.h"
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#include "GCNSubtarget.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/CodeGen/GlobalISel/Combiner.h"
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#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
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#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
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#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
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#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/IntrinsicsAMDGPU.h"
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#include "llvm/Target/TargetMachine.h"
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#define DEBUG_TYPE "amdgpu-regbank-combiner"
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using namespace llvm;
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using namespace MIPatternMatch;
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class AMDGPURegBankCombinerHelper {
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protected:
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MachineIRBuilder &B;
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MachineFunction &MF;
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MachineRegisterInfo &MRI;
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const GCNSubtarget &Subtarget;
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const RegisterBankInfo &RBI;
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const TargetRegisterInfo &TRI;
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const SIInstrInfo &TII;
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CombinerHelper &Helper;
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public:
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AMDGPURegBankCombinerHelper(MachineIRBuilder &B, CombinerHelper &Helper)
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: B(B), MF(B.getMF()), MRI(*B.getMRI()),
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Subtarget(MF.getSubtarget<GCNSubtarget>()),
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RBI(*Subtarget.getRegBankInfo()), TRI(*Subtarget.getRegisterInfo()),
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TII(*Subtarget.getInstrInfo()), Helper(Helper){};
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bool isVgprRegBank(Register Reg);
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Register getAsVgpr(Register Reg);
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struct MinMaxMedOpc {
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unsigned Min, Max, Med;
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};
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struct Med3MatchInfo {
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unsigned Opc;
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Register Val0, Val1, Val2;
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};
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MinMaxMedOpc getMinMaxPair(unsigned Opc);
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template <class m_Cst, typename CstTy>
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bool matchMed(MachineInstr &MI, MachineRegisterInfo &MRI, MinMaxMedOpc MMMOpc,
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Register &Val, CstTy &K0, CstTy &K1);
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bool matchIntMinMaxToMed3(MachineInstr &MI, Med3MatchInfo &MatchInfo);
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bool matchFPMinMaxToMed3(MachineInstr &MI, Med3MatchInfo &MatchInfo);
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bool matchFPMinMaxToClamp(MachineInstr &MI, Register &Reg);
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bool matchFPMed3ToClamp(MachineInstr &MI, Register &Reg);
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void applyMed3(MachineInstr &MI, Med3MatchInfo &MatchInfo);
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void applyClamp(MachineInstr &MI, Register &Reg);
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private:
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SIModeRegisterDefaults getMode();
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bool getIEEE();
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bool getDX10Clamp();
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bool isFminnumIeee(const MachineInstr &MI);
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bool isFCst(MachineInstr *MI);
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bool isClampZeroToOne(MachineInstr *K0, MachineInstr *K1);
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};
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bool AMDGPURegBankCombinerHelper::isVgprRegBank(Register Reg) {
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return RBI.getRegBank(Reg, MRI, TRI)->getID() == AMDGPU::VGPRRegBankID;
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}
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Register AMDGPURegBankCombinerHelper::getAsVgpr(Register Reg) {
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if (isVgprRegBank(Reg))
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return Reg;
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// Search for existing copy of Reg to vgpr.
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for (MachineInstr &Use : MRI.use_instructions(Reg)) {
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Register Def = Use.getOperand(0).getReg();
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if (Use.getOpcode() == AMDGPU::COPY && isVgprRegBank(Def))
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return Def;
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}
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// Copy Reg to vgpr.
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Register VgprReg = B.buildCopy(MRI.getType(Reg), Reg).getReg(0);
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MRI.setRegBank(VgprReg, RBI.getRegBank(AMDGPU::VGPRRegBankID));
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return VgprReg;
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}
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AMDGPURegBankCombinerHelper::MinMaxMedOpc
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AMDGPURegBankCombinerHelper::getMinMaxPair(unsigned Opc) {
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switch (Opc) {
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default:
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llvm_unreachable("Unsupported opcode");
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case AMDGPU::G_SMAX:
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case AMDGPU::G_SMIN:
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return {AMDGPU::G_SMIN, AMDGPU::G_SMAX, AMDGPU::G_AMDGPU_SMED3};
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case AMDGPU::G_UMAX:
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case AMDGPU::G_UMIN:
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return {AMDGPU::G_UMIN, AMDGPU::G_UMAX, AMDGPU::G_AMDGPU_UMED3};
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case AMDGPU::G_FMAXNUM:
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case AMDGPU::G_FMINNUM:
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return {AMDGPU::G_FMINNUM, AMDGPU::G_FMAXNUM, AMDGPU::G_AMDGPU_FMED3};
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case AMDGPU::G_FMAXNUM_IEEE:
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case AMDGPU::G_FMINNUM_IEEE:
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return {AMDGPU::G_FMINNUM_IEEE, AMDGPU::G_FMAXNUM_IEEE,
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AMDGPU::G_AMDGPU_FMED3};
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}
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}
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template <class m_Cst, typename CstTy>
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bool AMDGPURegBankCombinerHelper::matchMed(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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MinMaxMedOpc MMMOpc, Register &Val,
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CstTy &K0, CstTy &K1) {
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// 4 operand commutes of: min(max(Val, K0), K1).
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// Find K1 from outer instr: min(max(...), K1) or min(K1, max(...)).
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// Find K0 and Val from inner instr: max(K0, Val) or max(Val, K0).
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// 4 operand commutes of: max(min(Val, K1), K0).
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// Find K0 from outer instr: max(min(...), K0) or max(K0, min(...)).
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// Find K1 and Val from inner instr: min(K1, Val) or min(Val, K1).
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return mi_match(
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MI, MRI,
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m_any_of(
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m_CommutativeBinOp(
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MMMOpc.Min, m_CommutativeBinOp(MMMOpc.Max, m_Reg(Val), m_Cst(K0)),
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m_Cst(K1)),
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m_CommutativeBinOp(
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MMMOpc.Max, m_CommutativeBinOp(MMMOpc.Min, m_Reg(Val), m_Cst(K1)),
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m_Cst(K0))));
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}
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bool AMDGPURegBankCombinerHelper::matchIntMinMaxToMed3(
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MachineInstr &MI, Med3MatchInfo &MatchInfo) {
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Register Dst = MI.getOperand(0).getReg();
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if (!isVgprRegBank(Dst))
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return false;
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// med3 for i16 is only available on gfx9+, and not available for v2i16.
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LLT Ty = MRI.getType(Dst);
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if ((Ty != LLT::scalar(16) || !Subtarget.hasMed3_16()) &&
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Ty != LLT::scalar(32))
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return false;
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MinMaxMedOpc OpcodeTriple = getMinMaxPair(MI.getOpcode());
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Register Val;
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std::optional<ValueAndVReg> K0, K1;
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// Match min(max(Val, K0), K1) or max(min(Val, K1), K0). Then see if K0 <= K1.
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if (!matchMed<GCstAndRegMatch>(MI, MRI, OpcodeTriple, Val, K0, K1))
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return false;
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if (OpcodeTriple.Med == AMDGPU::G_AMDGPU_SMED3 && K0->Value.sgt(K1->Value))
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return false;
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if (OpcodeTriple.Med == AMDGPU::G_AMDGPU_UMED3 && K0->Value.ugt(K1->Value))
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return false;
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MatchInfo = {OpcodeTriple.Med, Val, K0->VReg, K1->VReg};
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return true;
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}
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// fmed3(NaN, K0, K1) = min(min(NaN, K0), K1)
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// ieee = true : min/max(SNaN, K) = QNaN, min/max(QNaN, K) = K
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// ieee = false : min/max(NaN, K) = K
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// clamp(NaN) = dx10_clamp ? 0.0 : NaN
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// Consider values of min(max(Val, K0), K1) and max(min(Val, K1), K0) as input.
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// Other operand commutes (see matchMed) give same result since min and max are
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// commutative.
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// Try to replace fp min(max(Val, K0), K1) or max(min(Val, K1), K0), KO<=K1
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// with fmed3(Val, K0, K1) or clamp(Val). Clamp requires K0 = 0.0 and K1 = 1.0.
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// Val = SNaN only for ieee = true
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// fmed3(SNaN, K0, K1) = min(min(SNaN, K0), K1) = min(QNaN, K1) = K1
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// min(max(SNaN, K0), K1) = min(QNaN, K1) = K1
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// max(min(SNaN, K1), K0) = max(K1, K0) = K1
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// Val = NaN,ieee = false or Val = QNaN,ieee = true
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// fmed3(NaN, K0, K1) = min(min(NaN, K0), K1) = min(K0, K1) = K0
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// min(max(NaN, K0), K1) = min(K0, K1) = K0 (can clamp when dx10_clamp = true)
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// max(min(NaN, K1), K0) = max(K1, K0) = K1 != K0
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bool AMDGPURegBankCombinerHelper::matchFPMinMaxToMed3(
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MachineInstr &MI, Med3MatchInfo &MatchInfo) {
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Register Dst = MI.getOperand(0).getReg();
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LLT Ty = MRI.getType(Dst);
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// med3 for f16 is only available on gfx9+, and not available for v2f16.
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if ((Ty != LLT::scalar(16) || !Subtarget.hasMed3_16()) &&
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Ty != LLT::scalar(32))
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return false;
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auto OpcodeTriple = getMinMaxPair(MI.getOpcode());
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Register Val;
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std::optional<FPValueAndVReg> K0, K1;
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// Match min(max(Val, K0), K1) or max(min(Val, K1), K0). Then see if K0 <= K1.
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if (!matchMed<GFCstAndRegMatch>(MI, MRI, OpcodeTriple, Val, K0, K1))
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return false;
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if (K0->Value > K1->Value)
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return false;
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// For IEEE=false perform combine only when it's safe to assume that there are
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// no NaN inputs. Most often MI is marked with nnan fast math flag.
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// For IEEE=true consider NaN inputs. fmed3(NaN, K0, K1) is equivalent to
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// min(min(NaN, K0), K1). Safe to fold for min(max(Val, K0), K1) since inner
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// nodes(max/min) have same behavior when one input is NaN and other isn't.
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// Don't consider max(min(SNaN, K1), K0) since there is no isKnownNeverQNaN,
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// also post-legalizer inputs to min/max are fcanonicalized (never SNaN).
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if ((getIEEE() && isFminnumIeee(MI)) || isKnownNeverNaN(Dst, MRI)) {
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// Don't fold single use constant that can't be inlined.
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if ((!MRI.hasOneNonDBGUse(K0->VReg) || TII.isInlineConstant(K0->Value)) &&
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(!MRI.hasOneNonDBGUse(K1->VReg) || TII.isInlineConstant(K1->Value))) {
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MatchInfo = {OpcodeTriple.Med, Val, K0->VReg, K1->VReg};
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return true;
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}
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}
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return false;
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}
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bool AMDGPURegBankCombinerHelper::matchFPMinMaxToClamp(MachineInstr &MI,
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Register &Reg) {
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// Clamp is available on all types after regbankselect (f16, f32, f64, v2f16).
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auto OpcodeTriple = getMinMaxPair(MI.getOpcode());
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Register Val;
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std::optional<FPValueAndVReg> K0, K1;
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// Match min(max(Val, K0), K1) or max(min(Val, K1), K0).
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if (!matchMed<GFCstOrSplatGFCstMatch>(MI, MRI, OpcodeTriple, Val, K0, K1))
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return false;
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if (!K0->Value.isExactlyValue(0.0) || !K1->Value.isExactlyValue(1.0))
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return false;
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// For IEEE=false perform combine only when it's safe to assume that there are
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// no NaN inputs. Most often MI is marked with nnan fast math flag.
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// For IEEE=true consider NaN inputs. Only min(max(QNaN, 0.0), 1.0) evaluates
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// to 0.0 requires dx10_clamp = true.
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if ((getIEEE() && getDX10Clamp() && isFminnumIeee(MI) &&
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isKnownNeverSNaN(Val, MRI)) ||
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isKnownNeverNaN(MI.getOperand(0).getReg(), MRI)) {
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Reg = Val;
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return true;
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}
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return false;
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}
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// Replacing fmed3(NaN, 0.0, 1.0) with clamp. Requires dx10_clamp = true.
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// Val = SNaN only for ieee = true. It is important which operand is NaN.
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// min(min(SNaN, 0.0), 1.0) = min(QNaN, 1.0) = 1.0
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// min(min(SNaN, 1.0), 0.0) = min(QNaN, 0.0) = 0.0
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// min(min(0.0, 1.0), SNaN) = min(0.0, SNaN) = QNaN
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// Val = NaN,ieee = false or Val = QNaN,ieee = true
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// min(min(NaN, 0.0), 1.0) = min(0.0, 1.0) = 0.0
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// min(min(NaN, 1.0), 0.0) = min(1.0, 0.0) = 0.0
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// min(min(0.0, 1.0), NaN) = min(0.0, NaN) = 0.0
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bool AMDGPURegBankCombinerHelper::matchFPMed3ToClamp(MachineInstr &MI,
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Register &Reg) {
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if (MI.getIntrinsicID() != Intrinsic::amdgcn_fmed3)
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return false;
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// In llvm-ir, clamp is often represented as an intrinsic call to
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// @llvm.amdgcn.fmed3.f32(%Val, 0.0, 1.0). Check for other operand orders.
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MachineInstr *Src0 = getDefIgnoringCopies(MI.getOperand(2).getReg(), MRI);
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MachineInstr *Src1 = getDefIgnoringCopies(MI.getOperand(3).getReg(), MRI);
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MachineInstr *Src2 = getDefIgnoringCopies(MI.getOperand(4).getReg(), MRI);
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if (isFCst(Src0) && !isFCst(Src1))
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std::swap(Src0, Src1);
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if (isFCst(Src1) && !isFCst(Src2))
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std::swap(Src1, Src2);
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if (isFCst(Src0) && !isFCst(Src1))
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std::swap(Src0, Src1);
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if (!isClampZeroToOne(Src1, Src2))
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return false;
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Register Val = Src0->getOperand(0).getReg();
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auto isOp3Zero = [&]() {
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MachineInstr *Op3 = getDefIgnoringCopies(MI.getOperand(4).getReg(), MRI);
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if (Op3->getOpcode() == TargetOpcode::G_FCONSTANT)
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return Op3->getOperand(1).getFPImm()->isExactlyValue(0.0);
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return false;
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};
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// For IEEE=false perform combine only when it's safe to assume that there are
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// no NaN inputs. Most often MI is marked with nnan fast math flag.
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// For IEEE=true consider NaN inputs. Requires dx10_clamp = true. Safe to fold
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// when Val could be QNaN. If Val can also be SNaN third input should be 0.0.
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if (isKnownNeverNaN(MI.getOperand(0).getReg(), MRI) ||
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(getIEEE() && getDX10Clamp() &&
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(isKnownNeverSNaN(Val, MRI) || isOp3Zero()))) {
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Reg = Val;
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return true;
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}
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return false;
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}
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void AMDGPURegBankCombinerHelper::applyClamp(MachineInstr &MI, Register &Reg) {
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B.setInstrAndDebugLoc(MI);
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B.buildInstr(AMDGPU::G_AMDGPU_CLAMP, {MI.getOperand(0)}, {Reg},
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MI.getFlags());
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MI.eraseFromParent();
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}
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void AMDGPURegBankCombinerHelper::applyMed3(MachineInstr &MI,
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Med3MatchInfo &MatchInfo) {
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B.setInstrAndDebugLoc(MI);
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B.buildInstr(MatchInfo.Opc, {MI.getOperand(0)},
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{getAsVgpr(MatchInfo.Val0), getAsVgpr(MatchInfo.Val1),
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getAsVgpr(MatchInfo.Val2)},
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MI.getFlags());
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MI.eraseFromParent();
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}
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SIModeRegisterDefaults AMDGPURegBankCombinerHelper::getMode() {
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return MF.getInfo<SIMachineFunctionInfo>()->getMode();
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}
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bool AMDGPURegBankCombinerHelper::getIEEE() { return getMode().IEEE; }
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bool AMDGPURegBankCombinerHelper::getDX10Clamp() { return getMode().DX10Clamp; }
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bool AMDGPURegBankCombinerHelper::isFminnumIeee(const MachineInstr &MI) {
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return MI.getOpcode() == AMDGPU::G_FMINNUM_IEEE;
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}
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bool AMDGPURegBankCombinerHelper::isFCst(MachineInstr *MI) {
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return MI->getOpcode() == AMDGPU::G_FCONSTANT;
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}
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bool AMDGPURegBankCombinerHelper::isClampZeroToOne(MachineInstr *K0,
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MachineInstr *K1) {
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if (isFCst(K0) && isFCst(K1)) {
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const ConstantFP *KO_FPImm = K0->getOperand(1).getFPImm();
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const ConstantFP *K1_FPImm = K1->getOperand(1).getFPImm();
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return (KO_FPImm->isExactlyValue(0.0) && K1_FPImm->isExactlyValue(1.0)) ||
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(KO_FPImm->isExactlyValue(1.0) && K1_FPImm->isExactlyValue(0.0));
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}
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return false;
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}
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class AMDGPURegBankCombinerHelperState {
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protected:
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CombinerHelper &Helper;
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AMDGPURegBankCombinerHelper &RegBankHelper;
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public:
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AMDGPURegBankCombinerHelperState(CombinerHelper &Helper,
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AMDGPURegBankCombinerHelper &RegBankHelper)
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: Helper(Helper), RegBankHelper(RegBankHelper) {}
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};
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#define AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_DEPS
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#include "AMDGPUGenRegBankGICombiner.inc"
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#undef AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_DEPS
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namespace {
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#define AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_H
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#include "AMDGPUGenRegBankGICombiner.inc"
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#undef AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_H
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class AMDGPURegBankCombinerInfo final : public CombinerInfo {
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GISelKnownBits *KB;
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MachineDominatorTree *MDT;
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public:
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AMDGPUGenRegBankCombinerHelperRuleConfig GeneratedRuleCfg;
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AMDGPURegBankCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize,
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const AMDGPULegalizerInfo *LI,
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GISelKnownBits *KB, MachineDominatorTree *MDT)
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: CombinerInfo(/*AllowIllegalOps*/ false, /*ShouldLegalizeIllegal*/ true,
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/*LegalizerInfo*/ LI, EnableOpt, OptSize, MinSize),
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KB(KB), MDT(MDT) {
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if (!GeneratedRuleCfg.parseCommandLineOption())
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report_fatal_error("Invalid rule identifier");
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}
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bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
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MachineIRBuilder &B) const override;
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};
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bool AMDGPURegBankCombinerInfo::combine(GISelChangeObserver &Observer,
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MachineInstr &MI,
|
|
MachineIRBuilder &B) const {
|
|
CombinerHelper Helper(Observer, B, /* IsPreLegalize*/ false, KB, MDT);
|
|
AMDGPURegBankCombinerHelper RegBankHelper(B, Helper);
|
|
AMDGPUGenRegBankCombinerHelper Generated(GeneratedRuleCfg, Helper,
|
|
RegBankHelper);
|
|
|
|
if (Generated.tryCombineAll(Observer, MI, B))
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
#define AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_CPP
|
|
#include "AMDGPUGenRegBankGICombiner.inc"
|
|
#undef AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_CPP
|
|
|
|
// Pass boilerplate
|
|
// ================
|
|
|
|
class AMDGPURegBankCombiner : public MachineFunctionPass {
|
|
public:
|
|
static char ID;
|
|
|
|
AMDGPURegBankCombiner(bool IsOptNone = false);
|
|
|
|
StringRef getPassName() const override {
|
|
return "AMDGPURegBankCombiner";
|
|
}
|
|
|
|
bool runOnMachineFunction(MachineFunction &MF) override;
|
|
|
|
void getAnalysisUsage(AnalysisUsage &AU) const override;
|
|
private:
|
|
bool IsOptNone;
|
|
};
|
|
} // end anonymous namespace
|
|
|
|
void AMDGPURegBankCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
|
|
AU.addRequired<TargetPassConfig>();
|
|
AU.setPreservesCFG();
|
|
getSelectionDAGFallbackAnalysisUsage(AU);
|
|
AU.addRequired<GISelKnownBitsAnalysis>();
|
|
AU.addPreserved<GISelKnownBitsAnalysis>();
|
|
if (!IsOptNone) {
|
|
AU.addRequired<MachineDominatorTree>();
|
|
AU.addPreserved<MachineDominatorTree>();
|
|
}
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
|
}
|
|
|
|
AMDGPURegBankCombiner::AMDGPURegBankCombiner(bool IsOptNone)
|
|
: MachineFunctionPass(ID), IsOptNone(IsOptNone) {
|
|
initializeAMDGPURegBankCombinerPass(*PassRegistry::getPassRegistry());
|
|
}
|
|
|
|
bool AMDGPURegBankCombiner::runOnMachineFunction(MachineFunction &MF) {
|
|
if (MF.getProperties().hasProperty(
|
|
MachineFunctionProperties::Property::FailedISel))
|
|
return false;
|
|
auto *TPC = &getAnalysis<TargetPassConfig>();
|
|
const Function &F = MF.getFunction();
|
|
bool EnableOpt =
|
|
MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
|
|
|
|
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
|
|
const AMDGPULegalizerInfo *LI
|
|
= static_cast<const AMDGPULegalizerInfo *>(ST.getLegalizerInfo());
|
|
|
|
GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
|
|
MachineDominatorTree *MDT =
|
|
IsOptNone ? nullptr : &getAnalysis<MachineDominatorTree>();
|
|
AMDGPURegBankCombinerInfo PCInfo(EnableOpt, F.hasOptSize(),
|
|
F.hasMinSize(), LI, KB, MDT);
|
|
Combiner C(PCInfo, TPC);
|
|
return C.combineMachineInstrs(MF, /*CSEInfo*/ nullptr);
|
|
}
|
|
|
|
char AMDGPURegBankCombiner::ID = 0;
|
|
INITIALIZE_PASS_BEGIN(AMDGPURegBankCombiner, DEBUG_TYPE,
|
|
"Combine AMDGPU machine instrs after regbankselect",
|
|
false, false)
|
|
INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
|
|
INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis)
|
|
INITIALIZE_PASS_END(AMDGPURegBankCombiner, DEBUG_TYPE,
|
|
"Combine AMDGPU machine instrs after regbankselect", false,
|
|
false)
|
|
|
|
namespace llvm {
|
|
FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone) {
|
|
return new AMDGPURegBankCombiner(IsOptNone);
|
|
}
|
|
} // end namespace llvm
|