baafc74ab0
The logic enabling the Arm SVE (and now SME) integration tests for various dialects, that may run under emulation, is now duplicated in several places. This patch moves the configuration to the top-level MLIR integration tests Lit config and renames the '%lli' substitution in contexts where it will run exclusively (ArmSVE, ArmSME) on AArch64 (and possibly under emulation) to '%lli_aarch64_cmd', and '%lli_host_or_aarch64_cmd' for contexts where it may run AArch64 (also possibly under emulation). The latter is for integration tests that have target-specific and target-agnostic codepaths such as SparseTensor, which supports scalable vectors. The two substitutions have the same effect but the names are different to convey this information. The '%lli_aarch64_cmd' substitution could be used in the SparseTensor tests but that would be a misnomer if the host were x86 and the MLIR_RUN_SVE_TESTS=OFF. The reason for renaming the '%lli' substitution is to not prevent running other target-specific integration tests at the same time, since the same substitution '%lli' is used for lli in other integration tests: * mlir/test/Integration/Dialect/Vector/CPU/X86Vector - (AVX emulation via Intel SDE) * mlir/test/Integration/Dialect/Vector/CPU/AMX - (AMX emulation via Intel SDE) * mlir/test/Integration/Dialect/LLVMIR/CPU/test-vp-intrinsic.mlir - (RISCV emulation via QEMU if supported, native otherwise) and substituting '%lli' at the top-level with Arm specific logic would override this. Reviewed By: awarzynski Differential Revision: https://reviews.llvm.org/D148929
119 lines
4.0 KiB
MLIR
119 lines
4.0 KiB
MLIR
// DEFINE: %{option} = enable-runtime-library=true
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// DEFINE: %{compile} = mlir-opt %s --sparse-compiler=%{option}
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// DEFINE: %{run} = mlir-cpu-runner \
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// DEFINE: -e entry -entry-point-result=void \
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// DEFINE: -shared-libs=%mlir_c_runner_utils | \
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// DEFINE: FileCheck %s
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//
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// RUN: %{compile} | %{run}
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//
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// Do the same run, but now with direct IR generation.
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// REDEFINE: %{option} = "enable-runtime-library=false enable-buffer-initialization=true"
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// RUN: %{compile} | %{run}
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// Do the same run, but now with direct IR generation and, if available, VLA
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// vectorization.
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// REDEFINE: %{option} = "enable-runtime-library=false enable-buffer-initialization=true vl=4 enable-arm-sve=%ENABLE_VLA"
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// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \
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// REDEFINE: --entry-function=entry_lli \
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// REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \
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// REDEFINE: %VLA_ARCH_ATTR_OPTIONS \
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// REDEFINE: --dlopen=%mlir_native_utils_lib_dir/libmlir_c_runner_utils%shlibext | \
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// REDEFINE: FileCheck %s
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// RUN: %{compile} | mlir-translate -mlir-to-llvmir | %{run}
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#SparseVector = #sparse_tensor.encoding<{ dimLevelType = [ "compressed" ] }>
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#trait_op = {
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indexing_maps = [
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affine_map<(i) -> (i)>, // a
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affine_map<(i) -> (i)> // x (out)
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],
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iterator_types = ["parallel"],
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doc = "x(i) = OP a(i)"
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}
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module {
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// Performs sign operation (using semi-ring unary op)
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// with semantics that
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// > 0 : +1.0
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// < 0 : -1.0
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// +Inf: +1.0
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// -Inf: -1.0
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// +NaN: +NaN
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// -NaN: -NaN
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// +0.0: +0.0
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// -0.0: -0.0
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func.func @sparse_sign(%arg0: tensor<?xf64, #SparseVector>)
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-> tensor<?xf64, #SparseVector> {
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%c0 = arith.constant 0 : index
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%d = tensor.dim %arg0, %c0 : tensor<?xf64, #SparseVector>
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%xin = bufferization.alloc_tensor(%d) : tensor<?xf64, #SparseVector>
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%0 = linalg.generic #trait_op
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ins(%arg0: tensor<?xf64, #SparseVector>)
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outs(%xin: tensor<?xf64, #SparseVector>) {
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^bb0(%a: f64, %x: f64) :
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%result = sparse_tensor.unary %a : f64 to f64
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present={
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^bb1(%s: f64):
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%z = arith.constant 0.0 : f64
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%1 = arith.cmpf one, %s, %z : f64
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%2 = arith.uitofp %1 : i1 to f64
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%3 = math.copysign %2, %s : f64
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%4 = arith.cmpf uno, %s, %s : f64
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%5 = arith.select %4, %s, %3 : f64
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sparse_tensor.yield %5 : f64
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}
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absent={}
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linalg.yield %result : f64
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} -> tensor<?xf64, #SparseVector>
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return %0 : tensor<?xf64, #SparseVector>
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}
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// Driver method to call and verify sign kernel.
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func.func @entry() {
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%c0 = arith.constant 0 : index
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%du = arith.constant 0.0 : f64
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%pnan = arith.constant 0x7FF0000001000000 : f64
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%nnan = arith.constant 0xFFF0000001000000 : f64
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%pinf = arith.constant 0x7FF0000000000000 : f64
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%ninf = arith.constant 0xFFF0000000000000 : f64
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// Setup sparse vector.
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%v1 = arith.constant sparse<
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[ [0], [3], [5], [11], [13], [17], [18], [20], [21], [28], [29], [31] ],
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[ -1.5, 1.5, -10.2, 11.3, 1.0, -1.0,
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0x7FF0000001000000, // +NaN
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0xFFF0000001000000, // -NaN
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0x7FF0000000000000, // +Inf
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0xFFF0000000000000, // -Inf
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-0.0, // -Zero
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0.0 // +Zero
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]
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> : tensor<32xf64>
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%sv1 = sparse_tensor.convert %v1
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: tensor<32xf64> to tensor<?xf64, #SparseVector>
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// Call sign kernel.
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%0 = call @sparse_sign(%sv1) : (tensor<?xf64, #SparseVector>)
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-> tensor<?xf64, #SparseVector>
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//
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// Verify the results.
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//
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// CHECK: ( -1, 1, -1, 1, 1, -1, nan, -nan, 1, -1, -0, 0, 0 )
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//
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%1 = sparse_tensor.values %0 : tensor<?xf64, #SparseVector> to memref<?xf64>
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%2 = vector.transfer_read %1[%c0], %du: memref<?xf64>, vector<13xf64>
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vector.print %2 : vector<13xf64>
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// Release the resources.
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bufferization.dealloc_tensor %sv1 : tensor<?xf64, #SparseVector>
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bufferization.dealloc_tensor %0 : tensor<?xf64, #SparseVector>
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return
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}
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}
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