513e0c0ea4
Just fix the crash for now by not doing the optimization since figuring out how to properly convert the bits for an arbitrary struct is a pain. Also fix a crash when there is only an empty struct argument. llvm-svn: 335827
270 lines
9.8 KiB
C++
270 lines
9.8 KiB
C++
//===-- AMDGPULowerKernelArguments.cpp ------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This pass replaces accesses to kernel arguments with loads from
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/// offsets from the kernarg base pointer.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "AMDGPUTargetMachine.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Analysis/DivergenceAnalysis.h"
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#include "llvm/Analysis/Loads.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/BasicBlock.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/InstrTypes.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/IR/MDBuilder.h"
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#include "llvm/IR/Metadata.h"
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#include "llvm/IR/Operator.h"
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#include "llvm/IR/Type.h"
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#include "llvm/IR/Value.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/Casting.h"
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#define DEBUG_TYPE "amdgpu-lower-kernel-arguments"
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using namespace llvm;
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namespace {
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class AMDGPULowerKernelArguments : public FunctionPass{
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public:
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static char ID;
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AMDGPULowerKernelArguments() : FunctionPass(ID) {}
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bool runOnFunction(Function &F) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<TargetPassConfig>();
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AU.setPreservesAll();
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}
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};
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} // end anonymous namespace
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bool AMDGPULowerKernelArguments::runOnFunction(Function &F) {
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CallingConv::ID CC = F.getCallingConv();
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if (CC != CallingConv::AMDGPU_KERNEL || F.arg_empty())
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return false;
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auto &TPC = getAnalysis<TargetPassConfig>();
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const TargetMachine &TM = TPC.getTM<TargetMachine>();
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const SISubtarget &ST = TM.getSubtarget<SISubtarget>(F);
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LLVMContext &Ctx = F.getParent()->getContext();
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const DataLayout &DL = F.getParent()->getDataLayout();
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BasicBlock &EntryBlock = *F.begin();
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IRBuilder<> Builder(&*EntryBlock.begin());
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SmallVector<Type *, 16> ArgTypes;
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for (Argument &Arg : F.args()) {
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Type *ArgTy = Arg.getType();
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unsigned Size = DL.getTypeStoreSizeInBits(ArgTy);
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bool IsExtArg = Size < 32 && (Arg.hasZExtAttr() || Arg.hasSExtAttr()) &&
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!ST.isAmdHsaOS();
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// Clover seems to always pad i8/i16 to i32, but doesn't properly align
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// them?
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// Make sure the struct elements have correct size and alignment for ext
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// args. These seem to be padded up to 4-bytes but not correctly aligned.
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ArgTypes.push_back(
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IsExtArg ? ArrayType::get(ArgTy, 32 / Size) : Arg.getType());
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}
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StructType *ArgStructTy = StructType::create(Ctx, ArgTypes, F.getName());
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const StructLayout *Layout = DL.getStructLayout(ArgStructTy);
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// Minimum alignment for kern segment is 16.
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unsigned KernArgBaseAlign = std::max(16u, DL.getABITypeAlignment(ArgStructTy));
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const uint64_t BaseOffset = ST.getExplicitKernelArgOffset(F);
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// FIXME: Alignment is broken broken with explicit arg offset.;
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const uint64_t TotalKernArgSize = BaseOffset +
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ST.getKernArgSegmentSize(F, DL.getTypeAllocSize(ArgStructTy));
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if (TotalKernArgSize == 0)
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return false;
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CallInst *KernArgSegment =
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Builder.CreateIntrinsic(Intrinsic::amdgcn_kernarg_segment_ptr, nullptr,
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F.getName() + ".kernarg.segment");
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KernArgSegment->addAttribute(AttributeList::ReturnIndex, Attribute::NonNull);
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KernArgSegment->addAttribute(AttributeList::ReturnIndex,
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Attribute::getWithDereferenceableBytes(Ctx, TotalKernArgSize));
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KernArgSegment->addAttribute(AttributeList::ReturnIndex,
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Attribute::getWithAlignment(Ctx, KernArgBaseAlign));
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Value *KernArgBase = KernArgSegment;
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if (BaseOffset != 0) {
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KernArgBase = Builder.CreateConstInBoundsGEP1_64(KernArgBase, BaseOffset);
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KernArgBaseAlign = MinAlign(KernArgBaseAlign, BaseOffset);
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}
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unsigned AS = KernArgSegment->getType()->getPointerAddressSpace();
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Value *CastStruct = Builder.CreateBitCast(KernArgBase,
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ArgStructTy->getPointerTo(AS));
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for (Argument &Arg : F.args()) {
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if (Arg.use_empty())
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continue;
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Type *ArgTy = Arg.getType();
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if (PointerType *PT = dyn_cast<PointerType>(ArgTy)) {
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// FIXME: Hack. We rely on AssertZext to be able to fold DS addressing
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// modes on SI to know the high bits are 0 so pointer adds don't wrap. We
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// can't represent this with range metadata because it's only allowed for
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// integer types.
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if (PT->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
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ST.getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS)
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continue;
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// FIXME: We can replace this with equivalent alias.scope/noalias
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// metadata, but this appears to be a lot of work.
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if (Arg.hasNoAliasAttr())
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continue;
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}
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VectorType *VT = dyn_cast<VectorType>(ArgTy);
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bool IsV3 = VT && VT->getNumElements() == 3;
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VectorType *V4Ty = nullptr;
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unsigned Size = DL.getTypeSizeInBits(ArgTy);
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bool IsExtArg = Size < 32 && (Arg.hasZExtAttr() || Arg.hasSExtAttr()) &&
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!ST.isAmdHsaOS();
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int64_t EltOffset = Layout->getElementOffset(Arg.getArgNo());
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int64_t AlignDownOffset = alignDown(EltOffset, 4);
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int64_t OffsetDiff = EltOffset - AlignDownOffset;
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unsigned AdjustedAlign = MinAlign(KernArgBaseAlign, AlignDownOffset);
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Value *ArgPtr;
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if (Size < 32 && !ArgTy->isAggregateType()) { // FIXME: Handle aggregate types
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// Since we don't have sub-dword scalar loads, avoid doing an extload by
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// loading earlier than the argument address, and extracting the relevant
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// bits.
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//
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// Additionally widen any sub-dword load to i32 even if suitably aligned,
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// so that CSE between different argument loads works easily.
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ArgPtr = Builder.CreateConstGEP1_64(KernArgBase, AlignDownOffset);
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ArgPtr = Builder.CreateBitCast(
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ArgPtr,
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Builder.getInt32Ty()->getPointerTo(AS),
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Arg.getName() + ".kernarg.offset.align.down");
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} else {
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ArgPtr = Builder.CreateStructGEP(CastStruct, Arg.getArgNo(),
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Arg.getName() + ".kernarg.offset");
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}
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assert((!IsExtArg || !IsV3) && "incompatible situation");
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if (IsV3 && Size >= 32) {
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V4Ty = VectorType::get(VT->getVectorElementType(), 4);
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// Use the hack that clang uses to avoid SelectionDAG ruining v3 loads
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ArgPtr = Builder.CreateBitCast(ArgPtr, V4Ty->getPointerTo(AS));
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}
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LoadInst *Load = Builder.CreateAlignedLoad(ArgPtr, AdjustedAlign);
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Load->setMetadata(LLVMContext::MD_invariant_load, MDNode::get(Ctx, {}));
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MDBuilder MDB(Ctx);
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if (isa<PointerType>(ArgTy)) {
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if (Arg.hasNonNullAttr())
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Load->setMetadata(LLVMContext::MD_nonnull, MDNode::get(Ctx, {}));
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uint64_t DerefBytes = Arg.getDereferenceableBytes();
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if (DerefBytes != 0) {
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Load->setMetadata(
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LLVMContext::MD_dereferenceable,
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MDNode::get(Ctx,
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MDB.createConstant(
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ConstantInt::get(Builder.getInt64Ty(), DerefBytes))));
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}
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uint64_t DerefOrNullBytes = Arg.getDereferenceableOrNullBytes();
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if (DerefOrNullBytes != 0) {
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Load->setMetadata(
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LLVMContext::MD_dereferenceable_or_null,
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MDNode::get(Ctx,
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MDB.createConstant(ConstantInt::get(Builder.getInt64Ty(),
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DerefOrNullBytes))));
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}
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unsigned ParamAlign = Arg.getParamAlignment();
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if (ParamAlign != 0) {
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Load->setMetadata(
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LLVMContext::MD_align,
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MDNode::get(Ctx,
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MDB.createConstant(ConstantInt::get(Builder.getInt64Ty(),
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ParamAlign))));
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}
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}
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// TODO: Convert noalias arg to !noalias
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if (Size < 32 && !ArgTy->isAggregateType()) {
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if (IsExtArg && OffsetDiff == 0) {
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Type *I32Ty = Builder.getInt32Ty();
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bool IsSext = Arg.hasSExtAttr();
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Metadata *LowAndHigh[] = {
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ConstantAsMetadata::get(
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ConstantInt::get(I32Ty, IsSext ? minIntN(Size) : 0)),
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ConstantAsMetadata::get(
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ConstantInt::get(I32Ty,
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IsSext ? maxIntN(Size) + 1 : maxUIntN(Size) + 1))
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};
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Load->setMetadata(LLVMContext::MD_range, MDNode::get(Ctx, LowAndHigh));
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}
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Value *ExtractBits = OffsetDiff == 0 ?
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Load : Builder.CreateLShr(Load, OffsetDiff * 8);
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IntegerType *ArgIntTy = Builder.getIntNTy(Size);
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Value *Trunc = Builder.CreateTrunc(ExtractBits, ArgIntTy);
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Value *NewVal = Builder.CreateBitCast(Trunc, ArgTy,
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Arg.getName() + ".load");
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Arg.replaceAllUsesWith(NewVal);
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} else if (IsV3) {
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Value *Shuf = Builder.CreateShuffleVector(Load, UndefValue::get(V4Ty),
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{0, 1, 2},
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Arg.getName() + ".load");
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Arg.replaceAllUsesWith(Shuf);
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} else {
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Load->setName(Arg.getName() + ".load");
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Arg.replaceAllUsesWith(Load);
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}
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}
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return true;
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}
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INITIALIZE_PASS_BEGIN(AMDGPULowerKernelArguments, DEBUG_TYPE,
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"AMDGPU Lower Kernel Arguments", false, false)
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INITIALIZE_PASS_END(AMDGPULowerKernelArguments, DEBUG_TYPE, "AMDGPU Lower Kernel Arguments",
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false, false)
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char AMDGPULowerKernelArguments::ID = 0;
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FunctionPass *llvm::createAMDGPULowerKernelArgumentsPass() {
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return new AMDGPULowerKernelArguments();
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}
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