8c4a35237a
This replaces most argument uses with loads, but for now not all. The code in SelectionDAG for calling convention lowering is actively harmful for amdgpu_kernel. It attempts to split the argument types into register legal types, which results in low quality code for arbitary types. Since all kernel arguments are passed in memory, we just want the raw types. I've tried a couple of methods of mitigating this in SelectionDAG, but it's easier to just bypass this problem alltogether. It's possible to hack around the problem in the initial lowering, but the real problem is the DAG then expects to be able to use CopyToReg/CopyFromReg for uses of the arguments outside the block. Exposing the argument loads in the IR also has the advantage that the LoadStoreVectorizer can merge them. I'm not sure the best approach to dealing with the IR argument list is. The patch as-is just leaves the IR arguments in place, so all the existing code will still compute the same kernarg size and pointlessly lowers the arguments. Arguably the frontend should emit kernels with an empty argument list in the first place. Alternatively a dummy array could be inserted as a single argument just to reserve space. This does have some disadvantages. Local pointer kernel arguments can no longer have AssertZext placed on them as the equivalent !range metadata is not valid on pointer typed loads. This is mostly bad for SI which needs to know about the known bits in order to use the DS instruction offset, so in this case this is not done. More importantly, this skips noalias arguments since this pass does not yet convert this to the equivalent !alias.scope and !noalias metadata. Producing this metadata correctly seems to be tricky, although this logically is the same as inlining into a function which doesn't exist. Additionally, exposing these loads to the vectorizer may result in degraded aliasing information if a pointer load is merged with another argument load. I'm also not entirely sure this is preserving the current clover ABI, although I would greatly prefer if it would stop widening arguments and match the HSA ABI. As-is I think it is extending < 4-byte arguments to 4-bytes but doesn't align them to 4-bytes. llvm-svn: 335650
147 lines
4.0 KiB
LLVM
147 lines
4.0 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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;
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;
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; Most SALU instructions ignore control flow, so we need to make sure
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; they don't overwrite values from other blocks.
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; If the branch decision is made based on a value in an SGPR then all
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; threads will execute the same code paths, so we don't need to worry
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; about instructions in different blocks overwriting each other.
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; SI-LABEL: {{^}}sgpr_if_else_salu_br:
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; SI: s_add
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; SI: s_branch
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; SI: s_sub
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define amdgpu_kernel void @sgpr_if_else_salu_br(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
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entry:
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%0 = icmp eq i32 %a, 0
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br i1 %0, label %if, label %else
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if:
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%1 = sub i32 %b, %c
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br label %endif
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else:
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%2 = add i32 %d, %e
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br label %endif
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endif:
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%3 = phi i32 [%1, %if], [%2, %else]
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%4 = add i32 %3, %a
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store i32 %4, i32 addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}sgpr_if_else_salu_br_opt:
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; SI: s_cmp_lg_u32
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; SI: s_cbranch_scc0 [[IF:BB[0-9]+_[0-9]+]]
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; SI: ; %bb.1: ; %else
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; SI: s_load_dword [[LOAD0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x25
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; SI: s_load_dword [[LOAD1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2e
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; SI-NOT: add
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; SI: s_branch [[ENDIF:BB[0-9]+_[0-9]+]]
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; SI: [[IF]]: ; %if
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; SI: s_load_dword [[LOAD0]], s{{\[[0-9]+:[0-9]+\]}}, 0x13
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; SI: s_load_dword [[LOAD1]], s{{\[[0-9]+:[0-9]+\]}}, 0x1c
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; SI-NOT: add
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; SI: [[ENDIF]]: ; %endif
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; SI: s_add_i32 s{{[0-9]+}}, [[LOAD0]], [[LOAD1]]
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; SI: buffer_store_dword
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; SI-NEXT: s_endpgm
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define amdgpu_kernel void @sgpr_if_else_salu_br_opt(i32 addrspace(1)* %out, [8 x i32], i32 %a, [8 x i32], i32 %b, [8 x i32], i32 %c, [8 x i32], i32 %d, [8 x i32], i32 %e) {
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entry:
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%cmp0 = icmp eq i32 %a, 0
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br i1 %cmp0, label %if, label %else
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if:
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%add0 = add i32 %b, %c
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br label %endif
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else:
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%add1 = add i32 %d, %e
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br label %endif
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endif:
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%phi = phi i32 [%add0, %if], [%add1, %else]
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%add2 = add i32 %phi, %a
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store i32 %add2, i32 addrspace(1)* %out
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ret void
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}
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; The two S_ADD instructions should write to different registers, since
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; different threads will take different control flow paths.
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; SI-LABEL: {{^}}sgpr_if_else_valu_br:
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; SI: s_add_i32 [[SGPR:s[0-9]+]]
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; SI-NOT: s_add_i32 [[SGPR]]
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define amdgpu_kernel void @sgpr_if_else_valu_br(i32 addrspace(1)* %out, float %a, i32 %b, i32 %c, i32 %d, i32 %e) {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x() #0
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%tid_f = uitofp i32 %tid to float
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%tmp1 = fcmp ueq float %tid_f, 0.0
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br i1 %tmp1, label %if, label %else
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if:
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%tmp2 = add i32 %b, %c
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br label %endif
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else:
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%tmp3 = add i32 %d, %e
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br label %endif
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endif:
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%tmp4 = phi i32 [%tmp2, %if], [%tmp3, %else]
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store i32 %tmp4, i32 addrspace(1)* %out
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ret void
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}
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; FIXME: Should write to different SGPR pairs instead of copying to
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; VALU for i1 phi.
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; SI-LABEL: {{^}}sgpr_if_else_valu_cmp_phi_br:
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; SI: buffer_load_dword [[AVAL:v[0-9]+]]
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; SI: v_cmp_gt_i32_e32 [[CMP_IF:vcc]], 0, [[AVAL]]
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; SI: v_cndmask_b32_e64 [[V_CMP:v[0-9]+]], 0, -1, [[CMP_IF]]
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; SI: BB{{[0-9]+}}_2:
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; SI: buffer_load_dword [[AVAL:v[0-9]+]]
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; SI: v_cmp_eq_u32_e32 [[CMP_ELSE:vcc]], 0, [[AVAL]]
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; SI: v_cndmask_b32_e64 [[V_CMP]], 0, -1, [[CMP_ELSE]]
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; SI: v_cmp_ne_u32_e32 [[CMP_CMP:vcc]], 0, [[V_CMP]]
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; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP_CMP]]
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; SI: buffer_store_dword [[RESULT]]
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define amdgpu_kernel void @sgpr_if_else_valu_cmp_phi_br(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x() #0
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%tmp1 = icmp eq i32 %tid, 0
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br i1 %tmp1, label %if, label %else
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if:
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%gep.if = getelementptr i32, i32 addrspace(1)* %a, i32 %tid
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%a.val = load i32, i32 addrspace(1)* %gep.if
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%cmp.if = icmp eq i32 %a.val, 0
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br label %endif
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else:
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%gep.else = getelementptr i32, i32 addrspace(1)* %b, i32 %tid
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%b.val = load i32, i32 addrspace(1)* %gep.else
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%cmp.else = icmp slt i32 %b.val, 0
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br label %endif
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endif:
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%tmp4 = phi i1 [%cmp.if, %if], [%cmp.else, %else]
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%ext = sext i1 %tmp4 to i32
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store i32 %ext, i32 addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { readnone }
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