0d748b4d32
Changes VPReplicateRecipe to extract the last lane from an unconditional,
uniform store instruction. collectLoopUniforms will also add stores to
the list of uniform instructions where Legal->isUniformMemOp is true.
setCostBasedWideningDecision now sets the widening decision for
all uniform memory ops to Scalarize, where previously GatherScatter
may have been chosen for scalable stores.
This fixes an assert ("Cannot yet scalarize uniform stores") in
setCostBasedWideningDecision when we have a loop containing a
uniform i1 store and a scalable VF, which we cannot create a scatter for.
Reviewed By: sdesmalen, david-arm, fhahn
Differential Revision: https://reviews.llvm.org/D112725
23 lines
787 B
LLVM
23 lines
787 B
LLVM
; RUN: opt -S -loop-vectorize -mtriple=s390x-linux-gnu -tiny-trip-count-interleave-threshold=4 -vectorizer-min-trip-count=8 -force-vector-width=4 < %s | FileCheck %s
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; RUN: opt -S -passes=loop-vectorize -mtriple=s390x-linux-gnu -tiny-trip-count-interleave-threshold=4 -vectorizer-min-trip-count=8 -force-vector-width=4 < %s | FileCheck %s
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define i32 @main(i32 %arg, i8** nocapture readnone %arg1) #0 {
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;CHECK: vector.body:
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entry:
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%0 = alloca i8, align 1
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br label %loop
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loop:
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%storemerge.i.i = phi i8 [ 0, %entry ], [ %tmp12.i.i, %loop ]
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store i8 %storemerge.i.i, i8* %0, align 2
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%tmp8.i.i = icmp ult i8 %storemerge.i.i, 8
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%tmp12.i.i = add nuw nsw i8 %storemerge.i.i, 1
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br i1 %tmp8.i.i, label %loop, label %ret
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ret:
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ret i32 0
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}
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attributes #0 = { "target-cpu"="z13" }
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