82c1b136db
We already had the reasoning about uniform mem op loads; if the address is accessed at least once, we know the instruction doesn't need predicated to ensure fault safety. For stores, we do need to ensure that the values visible in memory are the same with and without predication. The easiest sub-case to check for is that all the values being stored are the same. Since we know that at least one lane is active, this tells us that the value must be visible. Warning on confusing terminology: "uniform" vs "uniform mem op" mean two different things here, and this patch is specific to the later. It would *not* be legal to make this same change for merely "uniform" operations. Differential Revision: https://reviews.llvm.org/D130637
105 lines
4.2 KiB
LLVM
105 lines
4.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes=loop-vectorize -force-vector-width=2 -S -prefer-predicate-over-epilogue=predicate-dont-vectorize %s | FileCheck %s
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; Test case for PR46525. There are two candidates to pick for
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; `udiv i64 %y, %add` when expanding SCEV expressions. Make sure we pick %div,
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; which dominates the vector loop.
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define void @test(i16 %x, i64 %y, i32* %ptr) {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CONV19:%.*]] = sext i16 [[X:%.*]] to i64
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; CHECK-NEXT: [[ADD:%.*]] = add i64 [[CONV19]], 492802768830814067
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; CHECK-NEXT: br label [[LOOP_PREHEADER:%.*]]
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; CHECK: loop.preheader:
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; CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[Y:%.*]], [[ADD]]
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; CHECK-NEXT: [[INC:%.*]] = add i64 [[DIV]], 1
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; CHECK-NEXT: [[TMP0:%.*]] = add nuw nsw i64 [[DIV]], 4
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; CHECK-NEXT: [[TMP1:%.*]] = udiv i64 [[TMP0]], [[INC]]
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; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1
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; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: [[N_RND_UP:%.*]] = add i64 [[TMP2]], 1
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], 2
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]]
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; CHECK-NEXT: [[IND_END:%.*]] = mul i64 [[N_VEC]], [[INC]]
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: store i32 0, i32* [[PTR:%.*]], align 4
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; CHECK-NEXT: store i32 0, i32* [[PTR]], align 4
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; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 2
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; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP3]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: br i1 true, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[LOOP_PREHEADER]] ]
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LOOP]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
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; CHECK-NEXT: store i32 0, i32* [[PTR]], align 4
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; CHECK-NEXT: [[V2:%.*]] = trunc i64 [[IV]] to i8
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; CHECK-NEXT: [[V3:%.*]] = add i8 [[V2]], 1
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; CHECK-NEXT: [[CMP15:%.*]] = icmp slt i8 [[V3]], 5
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], [[INC]]
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; CHECK-NEXT: br i1 [[CMP15]], label [[LOOP]], label [[LOOP_EXIT]], !llvm.loop [[LOOP2:![0-9]+]]
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; CHECK: loop.exit:
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; CHECK-NEXT: [[DIV_1:%.*]] = udiv i64 [[Y]], [[ADD]]
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; CHECK-NEXT: [[V1:%.*]] = add i64 [[DIV_1]], 1
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; CHECK-NEXT: br label [[LOOP_2:%.*]]
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; CHECK: loop.2:
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; CHECK-NEXT: [[IV_1:%.*]] = phi i64 [ [[IV_NEXT_1:%.*]], [[LOOP_2]] ], [ 0, [[LOOP_EXIT]] ]
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; CHECK-NEXT: [[IV_NEXT_1]] = add i64 [[IV_1]], [[V1]]
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; CHECK-NEXT: call void @use(i64 [[IV_NEXT_1]])
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; CHECK-NEXT: [[EC:%.*]] = icmp ult i64 [[IV_NEXT_1]], 200
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; CHECK-NEXT: br i1 [[EC]], label [[LOOP_2]], label [[LOOP_2_EXIT:%.*]]
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; CHECK: loop.2.exit:
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; CHECK-NEXT: [[C:%.*]] = call i1 @cond()
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; CHECK-NEXT: br i1 [[C]], label [[LOOP_PREHEADER]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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%conv19 = sext i16 %x to i64
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%add = add i64 %conv19, 492802768830814067
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br label %loop.preheader
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loop.preheader:
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%div = udiv i64 %y, %add
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%inc = add i64 %div, 1
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br label %loop
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loop:
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%iv = phi i64 [ %iv.next, %loop ], [ 0, %loop.preheader ]
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store i32 0, i32* %ptr, align 4
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%v2 = trunc i64 %iv to i8
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%v3 = add i8 %v2, 1
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%cmp15 = icmp slt i8 %v3, 5
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%iv.next = add i64 %iv, %inc
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br i1 %cmp15, label %loop, label %loop.exit
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loop.exit:
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%div.1 = udiv i64 %y, %add
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%v1 = add i64 %div.1, 1
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br label %loop.2
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loop.2:
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%iv.1 = phi i64 [ %iv.next.1, %loop.2 ], [ 0, %loop.exit ]
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%iv.next.1 = add i64 %iv.1, %v1
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call void @use(i64 %iv.next.1)
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%ec = icmp ult i64 %iv.next.1, 200
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br i1 %ec, label %loop.2, label %loop.2.exit
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loop.2.exit:
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%c = call i1 @cond()
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br i1 %c, label %loop.preheader, label %exit
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exit:
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ret void
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}
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declare void @use(i64)
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declare i1 @cond()
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