26f8f3db39
If we know we have stack objects, we reserve the registers that the private buffer resource and wave offset are passed and use them directly. If not, reserve the last 5 SGPRs just in case we need to spill. After register allocation, try to pick the next available registers instead of the last SGPRs, and then insert copies from the inputs to the reserved registers in the progloue. This also only selectively enables all of the input registers which are really required instead of always enabling them. llvm-svn: 254331
58 lines
2.3 KiB
LLVM
58 lines
2.3 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=ALL %s
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; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=ALL %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefix=GCNHSA -check-prefix=CIHSA -check-prefix=ALL %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefix=GCNHSA -check-prefix=VIHSA -check-prefix=ALL %s
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; FIXME: align on alloca seems to be ignored for private_segment_alignment
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; ALL-LABEL: {{^}}large_alloca_compute_shader:
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; GCN: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
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; GCN: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
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; GCN: s_mov_b32 s10, -1
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; CI: s_mov_b32 s11, 0x80f000
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; VI: s_mov_b32 s11, 0x800000
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; GCNHSA: .amd_kernel_code_t
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; GCNHSA: compute_pgm_rsrc2_scratch_en = 1
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; GCNHSA: compute_pgm_rsrc2_user_sgpr = 6
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; GCNHSA: compute_pgm_rsrc2_tgid_x_en = 1
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; GCNHSA: compute_pgm_rsrc2_tgid_y_en = 0
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; GCNHSA: compute_pgm_rsrc2_tgid_z_en = 0
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; GCNHSA: compute_pgm_rsrc2_tg_size_en = 0
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; GCNHSA: compute_pgm_rsrc2_tidig_comp_cnt = 0
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; GCNHSA: enable_sgpr_private_segment_buffer = 1
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; GCNHSA: enable_sgpr_dispatch_ptr = 0
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; GCNHSA: enable_sgpr_queue_ptr = 0
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; GCNHSA: enable_sgpr_kernarg_segment_ptr = 1
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; GCNHSA: enable_sgpr_dispatch_id = 0
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; GCNHSA: enable_sgpr_flat_scratch_init = 0
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; GCNHSA: enable_sgpr_private_segment_size = 0
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; GCNHSA: enable_sgpr_grid_workgroup_count_x = 0
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; GCNHSA: enable_sgpr_grid_workgroup_count_y = 0
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; GCNHSA: enable_sgpr_grid_workgroup_count_z = 0
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; GCNHSA: workitem_private_segment_byte_size = 0
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; GCNHSA: private_segment_alignment = 4
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; GCNHSA: .end_amd_kernel_code_t
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; GCNHSA: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], s7 offen
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; GCNHSA: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], s7 offen
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; Scratch size = alloca size + emergency stack slot
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; ALL: ; ScratchSize: 32772
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define void @large_alloca_compute_shader(i32 %x, i32 %y) #0 {
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%large = alloca [8192 x i32], align 4
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%gep = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 8191
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store volatile i32 %x, i32* %gep
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%gep1 = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 %y
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%val = load volatile i32, i32* %gep1
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store volatile i32 %val, i32 addrspace(1)* undef
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ret void
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}
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attributes #0 = { nounwind }
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