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clang-p2996/llvm/test/CodeGen/RISCV
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Yeting Kuo ad68586a37 [VP][RISCV] Add vp.ctpop and RISC-V support. 
The patch also adds expandVPCTPOP in TargetLowering to expand VP_CTPOP nodes.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D139920
2022-12-14 09:47:44 +08:00
..
GlobalISel
…
intrinsics
…
rvv
[VP][RISCV] Add vp.ctpop and RISC-V support.
2022-12-14 09:47:44 +08:00
add-before-shl.ll
[RISCV] Replace uses of hasStdExtC with COrZca.
2022-12-07 09:34:01 -08:00
add-imm.ll
…
addc-adde-sube-subc.ll
…
addcarry.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
addimm-mulimm.ll
…
addrspacecast.ll
…
aext-to-sext.ll
[RISCV] Teach getRegAllocationHints about compressible SRAI/SRLI.
2022-11-30 10:28:57 -08:00
align-loops.ll
…
align.ll
…
alloca.ll
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alu8.ll
…
alu16.ll
…
alu32.ll
…
alu64.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
analyze-branch.ll
…
and.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
arith-with-overflow.ll
…
atomic-cmpxchg-branch-on-result.ll
[RISCV] Avoid redundant branch-to-branch when expanding cmpxchg
2022-08-17 13:49:15 +01:00
atomic-cmpxchg-flag.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
atomic-cmpxchg.ll
…
atomic-fence.ll
…
atomic-load-store.ll
…
atomic-rmw.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
atomic-signext.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
attributes.ll
[RISCV] Add CodeGen support and MC testcase of RISCV Zca Extension
2022-11-22 17:22:26 +08:00
bitreverse-shift.ll
…
bittest.ll
[RISCV] Add ANDI to getRegAllocationHints.
2022-11-30 20:59:02 -08:00
blockaddress.ll
…
branch-relaxation.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
branch.ll
[RISCV] Add ANDI to getRegAllocationHints.
2022-11-30 20:59:02 -08:00
bswap-bitreverse.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
bswap-shift.ll
…
byval.ll
…
callee-saved-fpr32s.ll
…
callee-saved-fpr64s.ll
…
callee-saved-gprs.ll
…
calling-conv-half.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
calling-conv-ilp32-ilp32f-common.ll
…
calling-conv-ilp32-ilp32f-ilp32d-common.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
calling-conv-ilp32.ll
…
calling-conv-ilp32d.ll
…
calling-conv-ilp32f-ilp32d-common.ll
…
calling-conv-lp64-lp64f-common.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
calling-conv-lp64-lp64f-lp64d-common.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
calling-conv-lp64.ll
…
calling-conv-rv32f-ilp32.ll
…
calling-conv-sext-zext.ll
…
calling-conv-vector-float.ll
…
calls.ll
…
cmp-bool.ll
…
codemodel-lowering.ll
[RISCV] Extend the Merge Base Offset pass to handle AUIPC+ADDI
2022-08-01 11:30:02 +02:00
compress-float.ll
…
compress-inline-asm.ll
…
compress-opt-branch.ll
[RISCV] Optimization for using compressed beqz and bnez PR#56391
2022-10-06 09:33:32 -07:00
compress-opt-select.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
compress.ll
…
copy-frameindex.mir
…
copysign-casts.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
ctlz-cttz-ctpop.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
disable-tail-calls.ll
…
disjoint.ll
…
div_minsize.ll
[RISCV]Enable isIntDivCheap when attribute is minsize
2022-07-27 18:22:51 +08:00
div-by-constant.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
div-pow2.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
div.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
double-arith-strict.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
double-arith.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
double-bitmanip-dagcombines.ll
…
double-br-fcmp.ll
…
double-calling-conv.ll
…
double-convert-strict.ll
[RISCV] Optimize SELECT_CC when the true value of select is Constant
2022-10-18 09:24:17 +08:00
double-convert.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
double-fcmp-strict.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
double-fcmp.ll
…
double-frem.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
double-imm.ll
…
double-intrinsics-strict.ll
…
double-intrinsics.ll
[RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven.
2022-10-26 14:36:49 -07:00
double-isnan.ll
…
double-mem.ll
…
double-previous-failure.ll
[RISCV] Teach combineDeMorganOfBoolean to handle (and (xor X, 1), (not Y)).
2022-08-25 10:55:45 -07:00
double-round-conv-sat.ll
[RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect
2022-10-13 09:06:12 -07:00
double-round-conv.ll
[RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven.
2022-10-26 14:36:49 -07:00
double-select-fcmp.ll
[RISCV] Fold (sub C, (xor (setcc), 1)) -> (add (setcc), C-1).
2022-08-17 09:50:08 -07:00
double-select-icmp.ll
[RISCV] Add test coverage for (select (icmp X, Y), float, float). NFC
2022-08-16 21:28:26 -07:00
double-stack-spill-restore.ll
…
dwarf-eh.ll
…
early-clobber-tied-def-subreg-liveness.ll
[RISCV] Generate .cfi_def_cfa_expression for RVV stack adjustment
2022-12-06 12:45:59 +03:00
early-clobber-tied-def-subreg-liveness.mir
…
eh-dwarf-cfa.ll
…
elf-preemption.ll
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
exception-pointer-register.ll
…
fastcc-float.ll
…
fastcc-int.ll
…
fixups-diff.ll
…
fixups-relax-diff.ll
…
float-arith-strict.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
float-arith.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
float-bit-preserving-dagcombines.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
float-bitmanip-dagcombines.ll
…
float-br-fcmp.ll
…
float-convert-strict.ll
[RISCV] Optimize SELECT_CC when the true value of select is Constant
2022-10-18 09:24:17 +08:00
float-convert.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
float-fcmp-strict.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
float-fcmp.ll
…
float-frem.ll
…
float-imm.ll
…
float-intrinsics-strict.ll
…
float-intrinsics.ll
[RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven.
2022-10-26 14:36:49 -07:00
float-isnan.ll
…
float-mem.ll
…
float-round-conv-sat.ll
[RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven.
2022-10-26 14:36:49 -07:00
float-round-conv.ll
[RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven.
2022-10-26 14:36:49 -07:00
float-select-fcmp.ll
[RISCV] Fold (sub C, (xor (setcc), 1)) -> (add (setcc), C-1).
2022-08-17 09:50:08 -07:00
float-select-icmp.ll
[RISCV] Add test coverage for (select (icmp X, Y), float, float). NFC
2022-08-16 21:28:26 -07:00
flt-rounds.ll
…
fmax-fmin.ll
…
fold-addi-loadstore.ll
[RISCV] Extend the Merge Base Offset pass to handle AUIPC+ADDI
2022-08-01 11:30:02 +02:00
fold-vector-cmp.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
forced-atomics.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
fp16-promote.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
fp128.ll
…
fp-imm.ll
…
fpclamptosat_vec.ll
[RISCV] Generate .cfi_def_cfa_expression for RVV stack adjustment
2022-12-06 12:45:59 +03:00
fpclamptosat.ll
[RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect
2022-10-13 09:06:12 -07:00
fpenv.ll
[RISCV] Add shift amount operands of shift, rotate, and Zbs instructions to hasAllNBitUsers.
2022-10-24 22:07:22 -07:00
frame-info.ll
…
frame.ll
…
frameaddr-returnaddr.ll
…
frm-dependency.ll
…
get-register-invalid.ll
…
get-register-noreserve.ll
…
get-register-reserve.ll
…
get-setcc-result-type.ll
Recommit "[RISCV] Use setcc's original SDLoc when inverting it in performSUBCombine."
2022-08-16 15:51:07 -07:00
ghccc-nest.ll
[RISCV] Add support for static chain
2022-11-09 16:10:32 +08:00
ghccc-rv32.ll
…
ghccc-rv64.ll
…
global-merge-offset.ll
[RISCV] Add the GlobalMerge pass (disabled by default)
2022-09-08 18:40:38 -07:00
global-merge.ll
[RISCV] Add the GlobalMerge pass (disabled by default)
2022-09-08 18:40:38 -07:00
half-arith-strict.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
half-arith.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
half-bitmanip-dagcombines.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
half-br-fcmp.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
half-convert-strict.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
half-convert.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
half-fcmp-strict.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
half-fcmp.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
half-frem.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
half-imm.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
half-intrinsics.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
half-isnan.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
half-mem.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
half-round-conv-sat.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
half-round-conv.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
half-select-fcmp.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
half-select-icmp.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
hoist-global-addr-base.ll
[RISCV] Simplify test case from D130931. NFC
2022-08-01 16:50:56 -07:00
hwasan-check-memaccess.ll
[RISC-V][HWASAN] Add support for lowering HWASAN intrinsic for RISC-V
2022-08-28 21:22:13 +03:00
i32-icmp.ll
[RISCV] Teach RISCVMatInt to prefer li+slli over lui+addi(w) for compressibility.
2022-12-06 10:31:17 -08:00
i64-icmp.ll
[RISCV] Teach RISCVMatInt to prefer li+slli over lui+addi(w) for compressibility.
2022-12-06 10:31:17 -08:00
iabs.ll
[RISCV] Expand i32 abs to negw+max at isel.
2022-11-14 19:44:05 -08:00
imm-cse.ll
…
imm.ll
[RISCV] Use bseti for 2048 in RISCVMatInt when Zbs is enabled.
2022-12-07 20:14:22 -08:00
indirectbr.ll
…
init-array.ll
…
inline-asm-abi-names.ll
…
inline-asm-clobbers.ll
…
inline-asm-d-abi-names.ll
…
inline-asm-d-constraint-f.ll
…
inline-asm-f-abi-names.ll
…
inline-asm-f-constraint-f.ll
…
inline-asm-i-constraint-i1.ll
…
inline-asm-invalid.ll
…
inline-asm-S-constraint.ll
…
inline-asm-zfh-constraint-f.ll
…
inline-asm.ll
…
interrupt-attr-args-error.ll
…
interrupt-attr-callee.ll
…
interrupt-attr-invalid.ll
…
interrupt-attr-nocall.ll
…
interrupt-attr-ret-error.ll
…
interrupt-attr.ll
…
isel-optnone.ll
…
jumptable.ll
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
large-stack.ll
[RISCV] Share code for fixed offsets adjustRegs (thus materializing fewer constants)
2022-11-30 09:28:29 -08:00
legalize-fneg.ll
…
libcall-tail-calls.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
lit.local.cfg
…
live-sp.mir
…
local-stack-slot-allocation.ll
[RISCV] Fold low 12 bits into instruction during frame index elimination
2022-12-02 11:54:06 -08:00
loop-strength-reduce-add-cheaper-than-mul.ll
[RISCV] Adjust RV64I data layout by using n32:64 in layout string
2022-10-28 08:27:03 -07:00
loop-strength-reduce-loop-invar.ll
[RISCV] Adjust RV64I data layout by using n32:64 in layout string
2022-10-28 08:27:03 -07:00
lsr-legaladdimm.ll
…
machine-combiner-mir.ll
[MachineCombiner][RISCV] Add fmadd/fmsub/fnmsub instructions patterns
2022-11-17 13:24:04 +03:00
machine-combiner.ll
[MachineCombiner] Extend reassociation logic to handle inverse instructions
2022-12-07 13:50:28 +03:00
machine-cp.mir
…
machine-cse.ll
…
machine-outliner-cfi.mir
…
machine-outliner-patchable.ll
…
machine-outliner-position.mir
…
machine-outliner-throw.ll
…
machinelicm-address-pseudos.ll
[RISCV] Extend the Merge Base Offset pass to handle AUIPC+ADDI
2022-08-01 11:30:02 +02:00
machineoutliner-jumptable.mir
…
machineoutliner-pcrel-lo.mir
[RISCV] Don't outline pcrel-lo operand.
2022-08-24 21:47:46 +08:00
machineoutliner.mir
…
MachineSink-implicit-x0.mir
…
macro-fusion-lui-addi.ll
[RISCV] Teach RISCVMatInt to prefer li+slli over lui+addi(w) for compressibility.
2022-12-06 10:31:17 -08:00
make-compressible-for-store-address.mir
…
make-compressible-rv64.mir
…
make-compressible.mir
…
mattr-invalid-combination.ll
…
mem64.ll
…
mem.ll
…
memcpy-inline.ll
…
min-max.ll
[RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect
2022-10-13 09:06:12 -07:00
mir-target-flags.ll
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
miss-sp-restore-eh.ll
…
module-target-abi2.ll
…
module-target-abi3.ll
[RISCV] Generate correct ELF abi flag when empty .ll file has target-abi attribute
2022-08-26 14:39:39 +08:00
module-target-abi.ll
…
mul.ll
[RISCV] Teach RISCVMatInt to prefer li+slli over lui+addi(w) for compressibility.
2022-12-06 10:31:17 -08:00
musttail-call.ll
…
narrow-shl-cst.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
neg-abs.ll
[RISCV] Expand i32 abs to negw+max at isel.
2022-11-14 19:44:05 -08:00
nest-register.ll
[RISCV] Add support for static chain
2022-11-09 16:10:32 +08:00
nomerge.ll
…
O0-pipeline.ll
Use-after-return sanitizer binary metadata
2022-12-05 14:40:31 +01:00
O3-pipeline.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
option-nopic.ll
…
option-norelax.ll
…
option-norvc.ll
…
option-pic.ll
…
option-relax.ll
…
option-rvc.ll
…
optnone-store-no-combine.ll
…
out-of-reach-emergency-slot.mir
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
overflow-intrinsic-optimizations.ll
…
patchable-function-entry.ll
…
pic-models.ll
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
pr40333.ll
…
pr51206.ll
…
pr53662.mir
…
pr55201.ll
…
pr56110.ll
…
pr56457.ll
…
pr58025.ll
[RISCV][SelectionDAGBuilder] Fix crash when copying a v1f32 vector between basic blocks.
2022-09-28 10:13:35 -07:00
pr58286.ll
[RISCV] Fold low 12 bits into instruction during frame index elimination
2022-12-02 11:54:06 -08:00
pr58511.ll
[RISCV] Teach RISCVMatInt to prefer li+slli over lui+addi(w) for compressibility.
2022-12-06 10:31:17 -08:00
prefetch.ll
[IR] Update llvm.prefetch to match docs
2022-08-19 09:11:17 +01:00
readcyclecounter.ll
…
regalloc-last-chance-recoloring-failure.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
rem.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
remat.ll
…
reserved-reg-errors.ll
…
reserved-regs.ll
…
riscv-codegenprepare-asm.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
riscv-codegenprepare.ll
…
rotl-rotr.ll
[RISCV] Add ADD to getRegAllocationHints to improve to improve use of c.add.
2022-11-25 08:59:27 -08:00
rv32e.ll
…
rv32i-rv64i-float-double.ll
…
rv32i-rv64i-half.ll
…
rv32zba.ll
[RISCV] Add ADD to getRegAllocationHints to improve to improve use of c.add.
2022-11-25 08:59:27 -08:00
rv32zbb-intrinsic.ll
…
rv32zbb-zbkb.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
rv32zbb.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
rv32zbc-intrinsic.ll
…
rv32zbc-zbkc-intrinsic.ll
…
rv32zbkb-intrinsic.ll
…
rv32zbkb.ll
[RISCV] Teach getRegAllocationHints about compressible SRAI/SRLI.
2022-11-30 10:28:57 -08:00
rv32zbkx-intrinsic.ll
…
rv32zbs.ll
[RISCV] Teach RISCVMatInt to prefer li+slli over lui+addi(w) for compressibility.
2022-12-06 10:31:17 -08:00
rv32zknd-intrinsic.ll
…
rv32zkne-intrinsic.ll
…
rv32zknh-intrinsic.ll
…
rv32zksed-intrinsic.ll
…
rv32zksh-intrinsic.ll
…
rv64-large-stack.ll
…
rv64d-double-convert-strict.ll
…
rv64d-double-convert.ll
…
rv64f-float-convert-strict.ll
…
rv64f-float-convert.ll
…
rv64i-complex-float.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
rv64i-demanded-bits.ll
[RISCV] Use hasAllWUsers to recover XORI/ORI
2022-10-10 14:16:50 +08:00
rv64i-double-softfloat.ll
…
rv64i-exhaustive-w-insts.ll
…
rv64i-shift-sext.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
rv64i-single-softfloat.ll
…
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll
…
rv64m-exhaustive-w-insts.ll
…
rv64m-w-insts-legalization.ll
…
rv64zba.ll
[RISCV] Add isel patterns to select slli+shXadd.uw.
2022-11-21 09:32:51 -08:00
rv64zbb-intrinsic.ll
[RISCV] Remove support for the unratified Zbp extension.
2022-09-21 21:22:42 -07:00
rv64zbb-zbkb.ll
[RISCV] Add shift amount operands of shift, rotate, and Zbs instructions to hasAllNBitUsers.
2022-10-24 22:07:22 -07:00
rv64zbb.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
rv64zbc-intrinsic.ll
…
rv64zbc-zbkc-intrinsic.ll
…
rv64zbkb-intrinsic.ll
…
rv64zbkb.ll
[RISCV] Teach getRegAllocationHints about compressible SRAI/SRLI.
2022-11-30 10:28:57 -08:00
rv64zbkx-intrinsic.ll
…
rv64zbs.ll
[RISCV] Teach RISCVMatInt to prefer li+slli over lui+addi(w) for compressibility.
2022-12-06 10:31:17 -08:00
rv64zfh-half-convert-strict.ll
…
rv64zfh-half-convert.ll
…
rv64zfh-half-intrinsics.ll
…
rv64zfhmin-half-convert-strict.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
rv64zfhmin-half-convert.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
rv64zfhmin-half-intrinsics.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
rv64zknd-intrinsic.ll
…
rv64zknd-zkne-intrinsic.ll
…
rv64zkne-intrinsic.ll
…
rv64zknh-intrinsic.ll
…
rv64zksed-intrinsic.ll
…
rv64zksh-intrinsic.ll
…
sadd_sat_plus.ll
[RISCV] Remove support for the unratified Zbt extension.
2022-09-20 20:26:48 -07:00
sadd_sat.ll
[RISCV] Remove support for the unratified Zbt extension.
2022-09-20 20:26:48 -07:00
saverestore.ll
…
scalable-vector-struct.ll
…
sdata-limit-0.ll
…
sdata-limit-4.ll
…
sdata-limit-8.ll
…
sdata-local-sym.ll
…
select-and.ll
[RISCV] Remove support for the unratified Zbt extension.
2022-09-20 20:26:48 -07:00
select-bare.ll
[RISCV] Remove support for the unratified Zbt extension.
2022-09-20 20:26:48 -07:00
select-binop-identity.ll
[RISCV]Keep (select c, 0/-1, X) during PerformDAGCombine
2022-12-06 09:26:29 +08:00
select-cc.ll
[RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments.
2022-10-04 15:39:10 -07:00
select-const.ll
[RISCV] Branchless lowering for (select (x < 0), TrueConstant, FalseConstant) and (select (x >= 0), TrueConstant, FalseConstant)
2022-11-25 20:18:30 +08:00
select-constant-xor.ll
[RISCV] Teach getRegAllocationHints about compressible SRAI/SRLI.
2022-11-30 10:28:57 -08:00
select-optimize-multiple.ll
[RISCV] Add ANDI to getRegAllocationHints.
2022-11-30 20:59:02 -08:00
select-optimize-multiple.mir
[RISCV] Remove support for the unratified Zbt extension.
2022-09-20 20:26:48 -07:00
select-or.ll
[RISCV] Remove support for the unratified Zbt extension.
2022-09-20 20:26:48 -07:00
select.ll
[RISCV] Teach getRegAllocationHints about compressible SRAI/SRLI.
2022-11-30 10:28:57 -08:00
selectcc-to-shiftand.ll
[RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect
2022-10-13 09:06:12 -07:00
setcc-logic.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
sext-zext-trunc.ll
[RISCV] Remove C!=0 restriction from (sub C, (setcc x, y, eq/neq)) -> (add C-1, (setcc x, y, neq/eq)).
2022-08-16 14:49:52 -07:00
sextw-removal.ll
[RISCV] Add support for call returns to RISCVSExtWRemoval.
2022-12-13 09:09:13 -08:00
shadowcallstack.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
shift-and.ll
[RISCV] Make sure we always call tryShrinkShlLogicImm for ISD:AND during isel.
2022-10-22 14:30:13 -07:00
shift-masked-shamt.ll
[RISCV] Add shift amount operands of shift, rotate, and Zbs instructions to hasAllNBitUsers.
2022-10-24 22:07:22 -07:00
shifts.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
shl-demanded.ll
…
shlimm-addimm.ll
…
short-foward-branch-opt.ll
[RISCV] Add basic support for the sifive-7-series short forward branch optimization.
2022-10-17 13:56:22 -07:00
shrinkwrap.ll
…
shuffle-reverse.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
signbit-test.ll
[AArch64][RISCV][x86] add tests for masked val equality with 0; NFC
2022-12-06 11:34:48 -05:00
sink-icmp.ll
…
spill-fpr-scalar.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
split-offsets.ll
[RISCV] Add ADD to getRegAllocationHints to improve to improve use of c.add.
2022-11-25 08:59:27 -08:00
split-sp-adjust.ll
…
split-udiv-by-constant.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
split-urem-by-constant.ll
Recommit "[TargetLowering][RISCV][X86] Support even divisors in expandDIVREMByConstant."
2022-10-24 10:08:50 -07:00
srem-lkk.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
srem-seteq-illegal-types.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
srem-vector-lkk.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
ssub_sat_plus.ll
[RISCV] Remove support for the unratified Zbt extension.
2022-09-20 20:26:48 -07:00
ssub_sat.ll
[RISCV] Remove support for the unratified Zbt extension.
2022-09-20 20:26:48 -07:00
stack-folding.ll
[RISCV] Add sext.b/h and zext.b/h/w to RISCVInstrInfo::foldMemoryOperandImpl.
2022-07-21 14:54:58 -07:00
stack-realignment-with-variable-sized-objects.ll
…
stack-realignment.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
stack-slot-size.ll
…
stack-store-check.ll
…
subtarget-features-std-ext.ll
…
switch-width.ll
…
tagged-globals.ll
re-land [RISC-V][HWASAN] Support tagging global variables for RISC-V HWASAN
2022-12-13 15:51:51 +03:00
tail-calls.ll
…
target-abi-invalid.ll
…
target-abi-valid.ll
…
thread-pointer.ll
…
tls-models.ll
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
trunc-free.ll
[RISCV] Enable isTruncateFree in SDAG for i64->i32 on rv64.
2022-08-15 08:32:51 -07:00
uadd_sat_plus.ll
[RISCV] Add ADD to getRegAllocationHints to improve to improve use of c.add.
2022-11-25 08:59:27 -08:00
uadd_sat.ll
[RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect
2022-10-13 09:06:12 -07:00
umulo-128-legalisation-lowering.ll
[RISCV] Add ADD to getRegAllocationHints to improve to improve use of c.add.
2022-11-25 08:59:27 -08:00
unaligned-load-store.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
unfold-masked-merge-scalar-variablemask.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
unroll-loop-cse.ll
…
urem-lkk.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
urem-seteq-illegal-types.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
urem-vector-lkk.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
usub_sat_plus.ll
[RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect
2022-10-13 09:06:12 -07:00
usub_sat.ll
[RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect
2022-10-13 09:06:12 -07:00
vadd-vp-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vararg.ll
[RISCV] Fold low 12 bits into instruction during frame index elimination
2022-12-02 11:54:06 -08:00
vec3-setcc-crash.ll
[RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect
2022-10-13 09:06:12 -07:00
vector-abi.ll
…
verify-instr.mir
…
vlenb.ll
…
vmul-vp-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsub-vp-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
wide-mem.ll
…
xaluo.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
zext-with-load-is-free.ll
…
zfh-half-intrinsics-strict.ll
[LegalizeTypes][RISCV] Support f16 in ExpandIntRes_LLROUND_LLRINT.
2022-09-26 11:09:33 -07:00
zfh-half-intrinsics.ll
…
zfh-imm.ll
…
zfhmin-half-intrinsics-strict.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
zfhmin-half-intrinsics.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
zfhmin-imm.ll
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00
zmmul.ll
…