9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
149 lines
6.7 KiB
LLVM
149 lines
6.7 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_add_i16:
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; VI: flat_load_ushort [[A:v[0-9]+]]
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; VI: flat_load_ushort [[B:v[0-9]+]]
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; VI: v_add_u16_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
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; VI-NEXT: buffer_store_short [[ADD]]
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define amdgpu_kernel void @v_test_add_i16(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds i16, ptr addrspace(1) %out, i32 %tid
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%gep.in0 = getelementptr inbounds i16, ptr addrspace(1) %in0, i32 %tid
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%gep.in1 = getelementptr inbounds i16, ptr addrspace(1) %in1, i32 %tid
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%a = load volatile i16, ptr addrspace(1) %gep.in0
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%b = load volatile i16, ptr addrspace(1) %gep.in1
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%add = add i16 %a, %b
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store i16 %add, ptr addrspace(1) %out
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ret void
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}
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_add_i16_constant:
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; VI: flat_load_ushort [[A:v[0-9]+]]
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; VI: v_add_u16_e32 [[ADD:v[0-9]+]], 0x7b, [[A]]
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; VI-NEXT: buffer_store_short [[ADD]]
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define amdgpu_kernel void @v_test_add_i16_constant(ptr addrspace(1) %out, ptr addrspace(1) %in0) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds i16, ptr addrspace(1) %out, i32 %tid
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%gep.in0 = getelementptr inbounds i16, ptr addrspace(1) %in0, i32 %tid
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%a = load volatile i16, ptr addrspace(1) %gep.in0
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%add = add i16 %a, 123
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store i16 %add, ptr addrspace(1) %out
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ret void
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}
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_add_i16_neg_constant:
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; VI: flat_load_ushort [[A:v[0-9]+]]
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; VI: v_add_u16_e32 [[ADD:v[0-9]+]], 0xfcb3, [[A]]
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; VI-NEXT: buffer_store_short [[ADD]]
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define amdgpu_kernel void @v_test_add_i16_neg_constant(ptr addrspace(1) %out, ptr addrspace(1) %in0) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds i16, ptr addrspace(1) %out, i32 %tid
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%gep.in0 = getelementptr inbounds i16, ptr addrspace(1) %in0, i32 %tid
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%a = load volatile i16, ptr addrspace(1) %gep.in0
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%add = add i16 %a, -845
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store i16 %add, ptr addrspace(1) %out
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ret void
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}
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_add_i16_inline_neg1:
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; VI: flat_load_ushort [[A:v[0-9]+]]
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; VI: v_add_u16_e32 [[ADD:v[0-9]+]], -1, [[A]]
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; VI-NEXT: buffer_store_short [[ADD]]
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define amdgpu_kernel void @v_test_add_i16_inline_neg1(ptr addrspace(1) %out, ptr addrspace(1) %in0) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds i16, ptr addrspace(1) %out, i32 %tid
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%gep.in0 = getelementptr inbounds i16, ptr addrspace(1) %in0, i32 %tid
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%a = load volatile i16, ptr addrspace(1) %gep.in0
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%add = add i16 %a, -1
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store i16 %add, ptr addrspace(1) %out
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ret void
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}
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_add_i16_zext_to_i32:
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; VI: flat_load_ushort [[A:v[0-9]+]]
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; VI: flat_load_ushort [[B:v[0-9]+]]
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; VI: v_add_u16_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
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; VI-NEXT: buffer_store_dword [[ADD]]
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define amdgpu_kernel void @v_test_add_i16_zext_to_i32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds i32, ptr addrspace(1) %out, i32 %tid
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%gep.in0 = getelementptr inbounds i16, ptr addrspace(1) %in0, i32 %tid
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%gep.in1 = getelementptr inbounds i16, ptr addrspace(1) %in1, i32 %tid
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%a = load volatile i16, ptr addrspace(1) %gep.in0
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%b = load volatile i16, ptr addrspace(1) %gep.in1
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%add = add i16 %a, %b
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%ext = zext i16 %add to i32
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store i32 %ext, ptr addrspace(1) %out
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ret void
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}
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_add_i16_zext_to_i64:
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; VI: flat_load_ushort [[A:v[0-9]+]]
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; VI: flat_load_ushort [[B:v[0-9]+]]
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; VI-DAG: v_add_u16_e32 v[[ADD:[0-9]+]], [[A]], [[B]]
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; VI: buffer_store_dwordx2 v[[[ADD]]:{{[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0{{$}}
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define amdgpu_kernel void @v_test_add_i16_zext_to_i64(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds i64, ptr addrspace(1) %out, i32 %tid
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%gep.in0 = getelementptr inbounds i16, ptr addrspace(1) %in0, i32 %tid
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%gep.in1 = getelementptr inbounds i16, ptr addrspace(1) %in1, i32 %tid
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%a = load volatile i16, ptr addrspace(1) %gep.in0
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%b = load volatile i16, ptr addrspace(1) %gep.in1
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%add = add i16 %a, %b
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%ext = zext i16 %add to i64
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store i64 %ext, ptr addrspace(1) %out
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ret void
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}
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_add_i16_sext_to_i32:
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; VI: flat_load_ushort [[A:v[0-9]+]]
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; VI: flat_load_ushort [[B:v[0-9]+]]
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; VI: v_add_u16_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
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; VI-NEXT: v_bfe_i32 [[SEXT:v[0-9]+]], [[ADD]], 0, 16
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; VI-NEXT: buffer_store_dword [[SEXT]]
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define amdgpu_kernel void @v_test_add_i16_sext_to_i32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds i32, ptr addrspace(1) %out, i32 %tid
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%gep.in0 = getelementptr inbounds i16, ptr addrspace(1) %in0, i32 %tid
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%gep.in1 = getelementptr inbounds i16, ptr addrspace(1) %in1, i32 %tid
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%a = load i16, ptr addrspace(1) %gep.in0
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%b = load i16, ptr addrspace(1) %gep.in1
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%add = add i16 %a, %b
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%ext = sext i16 %add to i32
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store i32 %ext, ptr addrspace(1) %out
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ret void
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}
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_add_i16_sext_to_i64:
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; VI: flat_load_ushort [[A:v[0-9]+]]
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; VI: flat_load_ushort [[B:v[0-9]+]]
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; VI: v_add_u16_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
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; VI-NEXT: v_bfe_i32 v[[LO:[0-9]+]], [[ADD]], 0, 16
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; VI-NEXT: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
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; VI-NEXT: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
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define amdgpu_kernel void @v_test_add_i16_sext_to_i64(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds i64, ptr addrspace(1) %out, i32 %tid
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%gep.in0 = getelementptr inbounds i16, ptr addrspace(1) %in0, i32 %tid
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%gep.in1 = getelementptr inbounds i16, ptr addrspace(1) %in1, i32 %tid
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%a = load i16, ptr addrspace(1) %gep.in0
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%b = load i16, ptr addrspace(1) %gep.in1
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%add = add i16 %a, %b
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%ext = sext i16 %add to i64
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store i64 %ext, ptr addrspace(1) %out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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