9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
166 lines
8.8 KiB
LLVM
166 lines
8.8 KiB
LLVM
; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN %s
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; RUN: not llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s 2>&1 | FileCheck -strict-whitespace -check-prefix=ERR %s
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; ERR: error: <unknown>:0:0: in function test_export_compr_zeroes_v2f16 void (): intrinsic not supported on subtarget
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declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #0
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declare void @llvm.amdgcn.exp.compr.v2i16(i32, i32, <2 x i16>, <2 x i16>, i1, i1) #0
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; GCN-LABEL: {{^}}test_export_compr_zeroes_v2f16:
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; GCN: exp mrt0 off, off, off, off compr{{$}}
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; GCN: exp mrt0 off, off, off, off done compr{{$}}
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define amdgpu_kernel void @test_export_compr_zeroes_v2f16() #0 {
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call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> zeroinitializer, <2 x half> zeroinitializer, i1 false, i1 false)
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call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> zeroinitializer, <2 x half> zeroinitializer, i1 true, i1 false)
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ret void
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}
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; GCN-LABEL: {{^}}test_export_compr_en_src0_v2f16:
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; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x40003c00
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; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x44003800
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; GCN: exp mrt0 [[SRC0]], [[SRC0]], off, off done compr{{$}}
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define amdgpu_kernel void @test_export_compr_en_src0_v2f16() #0 {
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call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 3, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 true, i1 false)
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ret void
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}
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; GCN-LABEL: {{^}}test_export_compr_en_src1_v2f16:
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; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x40003c00
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; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x44003800
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; GCN: exp mrt0 off, off, [[SRC1]], [[SRC1]] done compr{{$}}
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define amdgpu_kernel void @test_export_compr_en_src1_v2f16() #0 {
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call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 12, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 true, i1 false)
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ret void
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}
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; GCN-LABEL: {{^}}test_export_compr_en_src0_src1_v2f16:
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; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x40003c00
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; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x44003800
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; GCN: exp mrt0 [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] done compr{{$}}
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define amdgpu_kernel void @test_export_compr_en_src0_src1_v2f16() #0 {
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call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 true, i1 false)
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ret void
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}
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; GCN-LABEL: {{^}}test_export_compr_en_invalid2_v2f16:
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; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x40003c00
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; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x44003800
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; GCN: exp mrt0 off, [[SRC0]], off, off done compr{{$}}
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define amdgpu_kernel void @test_export_compr_en_invalid2_v2f16() #0 {
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call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 2, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 true, i1 false)
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ret void
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}
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; GCN-LABEL: {{^}}test_export_compr_en_invalid10_v2f16:
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; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x40003c00
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; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x44003800
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; GCN: exp mrt0 off, [[SRC0]], off, [[SRC1]] done compr{{$}}
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define amdgpu_kernel void @test_export_compr_en_invalid10_v2f16() #0 {
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call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 10, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 true, i1 false)
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ret void
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}
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; GCN-LABEL: {{^}}test_export_compr_mrt7_v2f16:
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; GCN-DAG: v_mov_b32_e32 [[VHALF:v[0-9]+]], 0x38003800
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; GCN: exp mrt7 [[VHALF]], [[VHALF]], [[VHALF]], [[VHALF]] compr{{$}}
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; GCN: exp mrt7 [[VHALF]], [[VHALF]], [[VHALF]], [[VHALF]] done compr{{$}}
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define amdgpu_kernel void @test_export_compr_mrt7_v2f16() #0 {
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call void @llvm.amdgcn.exp.compr.v2f16(i32 7, i32 15, <2 x half> <half 0.5, half 0.5>, <2 x half> <half 0.5, half 0.5>, i1 false, i1 false)
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call void @llvm.amdgcn.exp.compr.v2f16(i32 7, i32 15, <2 x half> <half 0.5, half 0.5>, <2 x half> <half 0.5, half 0.5>, i1 true, i1 false)
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ret void
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}
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; GCN-LABEL: {{^}}test_export_compr_z_v2f16:
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; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x40003c00
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; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x44003800
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; GCN: exp mrtz [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] compr{{$}}
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; GCN: exp mrtz [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] done compr{{$}}
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define amdgpu_kernel void @test_export_compr_z_v2f16() #0 {
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call void @llvm.amdgcn.exp.compr.v2f16(i32 8, i32 15, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 false, i1 false)
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call void @llvm.amdgcn.exp.compr.v2f16(i32 8, i32 15, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 true, i1 false)
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ret void
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}
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; GCN-LABEL: {{^}}test_export_compr_vm_v2f16:
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; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x40003c00
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; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x44003800
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; GCN: exp mrt0 [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] compr vm{{$}}
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; GCN: exp mrt0 [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] done compr vm{{$}}
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define amdgpu_kernel void @test_export_compr_vm_v2f16() #0 {
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call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 false, i1 true)
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call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 true, i1 true)
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ret void
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}
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; GCN-LABEL: {{^}}test_export_compr_zeroes_v2i16:
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; GCN: exp mrt0 off, off, off, off compr{{$}}
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; GCN: exp mrt0 off, off, off, off done compr{{$}}
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define amdgpu_kernel void @test_export_compr_zeroes_v2i16() #0 {
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call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 0, <2 x i16> zeroinitializer, <2 x i16> zeroinitializer, i1 false, i1 false)
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call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 0, <2 x i16> zeroinitializer, <2 x i16> zeroinitializer, i1 true, i1 false)
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ret void
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}
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; GCN-LABEL: {{^}}test_export_compr_en_src0_v2i16:
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; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x20001
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; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x40005
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; GCN: exp mrt0 [[SRC0]], off, off, off done compr{{$}}
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define amdgpu_kernel void @test_export_compr_en_src0_v2i16() #0 {
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call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 1, <2 x i16> <i16 1, i16 2>, <2 x i16> <i16 5, i16 4>, i1 true, i1 false)
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ret void
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}
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; GCN-LABEL: {{^}}test_export_compr_en_src1_v2i16:
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; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x20001
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; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x40005
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; GCN: exp mrt0 off, off, [[SRC1]], [[SRC1]] done compr{{$}}
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define amdgpu_kernel void @test_export_compr_en_src1_v2i16() #0 {
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call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 12, <2 x i16> <i16 1, i16 2>, <2 x i16> <i16 5, i16 4>, i1 true, i1 false)
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ret void
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}
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; GCN-LABEL: {{^}}test_export_compr_en_src0_src1_v2i16:
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; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x20001
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; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x40005
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; GCN: exp mrt0 [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] done compr{{$}}
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define amdgpu_kernel void @test_export_compr_en_src0_src1_v2i16() #0 {
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call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 15, <2 x i16> <i16 1, i16 2>, <2 x i16> <i16 5, i16 4>, i1 true, i1 false)
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ret void
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}
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; GCN-LABEL: {{^}}test_export_compr_mrt7_v2i16:
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; GCN-DAG: v_mov_b32_e32 [[VI16:v[0-9]+]], 0x50005
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; GCN: exp mrt7 [[VI16]], [[VI16]], [[VI16]], [[VI16]] compr{{$}}
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; GCN: exp mrt7 [[VI16]], [[VI16]], [[VI16]], [[VI16]] done compr{{$}}
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define amdgpu_kernel void @test_export_compr_mrt7_v2i16() #0 {
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call void @llvm.amdgcn.exp.compr.v2i16(i32 7, i32 15, <2 x i16> <i16 5, i16 5>, <2 x i16> <i16 5, i16 5>, i1 false, i1 false)
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call void @llvm.amdgcn.exp.compr.v2i16(i32 7, i32 15, <2 x i16> <i16 5, i16 5>, <2 x i16> <i16 5, i16 5>, i1 true, i1 false)
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ret void
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}
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; GCN-LABEL: {{^}}test_export_compr_z_v2i16:
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; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x20001
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; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x40005
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; GCN: exp mrtz [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] compr{{$}}
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; GCN: exp mrtz [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] done compr{{$}}
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define amdgpu_kernel void @test_export_compr_z_v2i16() #0 {
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call void @llvm.amdgcn.exp.compr.v2i16(i32 8, i32 15, <2 x i16> <i16 1, i16 2>, <2 x i16> <i16 5, i16 4>, i1 false, i1 false)
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call void @llvm.amdgcn.exp.compr.v2i16(i32 8, i32 15, <2 x i16> <i16 1, i16 2>, <2 x i16> <i16 5, i16 4>, i1 true, i1 false)
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ret void
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}
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; GCN-LABEL: {{^}}test_export_compr_vm_v2i16:
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; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x20001
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; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x40005
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; GCN: exp mrt0 [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] compr vm{{$}}
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; GCN: exp mrt0 [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] done compr vm{{$}}
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define amdgpu_kernel void @test_export_compr_vm_v2i16() #0 {
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call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 15, <2 x i16> <i16 1, i16 2>, <2 x i16> <i16 5, i16 4>, i1 false, i1 true)
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call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 15, <2 x i16> <i16 1, i16 2>, <2 x i16> <i16 5, i16 4>, i1 true, i1 true)
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ret void
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}
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attributes #0 = { nounwind }
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