2f98c5febc
The ld might relax ADRP+ADD or ADRP+LDR sequences to the ADR+NOP, add the new case to the skipRelocation for aarch64. Vladislav Khmelevsky, Advanced Software Technology Lab, Huawei Differential Revision: https://reviews.llvm.org/D123334
17 lines
556 B
Plaintext
17 lines
556 B
Plaintext
// This test checks that the pointers to PLT are properly updated.
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// The test is using lld linker.
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// Non-PIE:
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RUN: %clang %cflags -no-pie %p/../Inputs/plt.c -fuse-ld=lld \
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RUN: -o %t.lld.exe -Wl,-q
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RUN: llvm-bolt %t.lld.exe -o %t.lld.bolt.exe -use-old-text=0 -lite=0
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RUN: %t.lld.bolt.exe | FileCheck %s
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// PIE:
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RUN: %clang %cflags -fPIC -pie %p/../Inputs/plt.c -fuse-ld=lld \
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RUN: -o %t.lld.pie.exe -Wl,-q
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RUN: llvm-bolt %t.lld.pie.exe -o %t.lld.bolt.pie.exe -use-old-text=0 -lite=0
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RUN: %t.lld.bolt.pie.exe | FileCheck %s
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CHECK: Test completed
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